diff options
author | Yilun Lin <yllin@google.com> | 2018-08-01 16:14:46 +0800 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2019-04-15 15:39:18 +0000 |
commit | c129add2a2711af4322622b0db7c419ac1739de6 (patch) | |
tree | 6ca9a326fb978b66cbb3d4fa9f609091959578b0 | |
parent | 99904bb1d117b7015c9af5ee445e6c17a6ca9631 (diff) | |
download | chrome-ec-c129add2a2711af4322622b0db7c419ac1739de6.tar.gz |
tcpc/mt6370: add MediaTek MT6370 TCPC driver.
BUG=b:80160923 b:111908397
BRANCH=None
TEST=make flash_ec BOARD=kukui
TEST=plug-in PD charger, check negotiate success, TCPC is sinking 5v/12v.
TEST=plug-in peripheral; pd dualrole on; check TCPC is sourcing.
Change-Id: I3587a7df40ae3a6254435d3cd133e1ee3000e36b
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1158264
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1566035
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
-rw-r--r-- | driver/build.mk | 1 | ||||
-rw-r--r-- | driver/tcpm/mt6370.c | 131 | ||||
-rw-r--r-- | driver/tcpm/mt6370.h | 179 | ||||
-rw-r--r-- | include/config.h | 1 |
4 files changed, 312 insertions, 0 deletions
diff --git a/driver/build.mk b/driver/build.mk index cbd5d9140b..874b55c3df 100644 --- a/driver/build.mk +++ b/driver/build.mk @@ -103,6 +103,7 @@ driver-$(CONFIG_THERMISTOR_NCP15WB)+=temp_sensor/thermistor_ncp15wb.o driver-$(CONFIG_USB_PD_TCPM_STUB)+=tcpm/stub.o driver-$(CONFIG_USB_PD_TCPM_TCPCI)+=tcpm/tcpci.o driver-$(CONFIG_USB_PD_TCPM_FUSB302)+=tcpm/fusb302.o +driver-$(CONFIG_USB_PD_TCPM_MT6370)+=tcpm/mt6370.o driver-$(CONFIG_USB_PD_TCPM_ITE83XX)+=tcpm/it83xx.o driver-$(CONFIG_USB_PD_TCPM_ANX3429)+=tcpm/anx74xx.o driver-$(CONFIG_USB_PD_TCPM_ANX740X)+=tcpm/anx74xx.o diff --git a/driver/tcpm/mt6370.c b/driver/tcpm/mt6370.c new file mode 100644 index 0000000000..a9881b34d1 --- /dev/null +++ b/driver/tcpm/mt6370.c @@ -0,0 +1,131 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * MT6370 TCPC Driver + */ + +#include "console.h" +#include "hooks.h" +#include "mt6370.h" +#include "task.h" +#include "tcpci.h" +#include "tcpm.h" +#include "timer.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +static int mt6370_init(int port) +{ + int rv; + + /* Software reset. */ + rv = tcpc_write(port, MT6370_REG_SWRESET, 1); + if (rv) + return rv; + + /* Need 1 ms for software reset. */ + msleep(1); + + /* The earliest point that we can do generic init. */ + rv = tcpci_tcpm_init(port); + + if (rv) + return rv; + + /* + * AUTO IDLE off, shipping off, select CK_300K from BICIO_320K, + * PD3.0 ext-msg on. + */ + rv = tcpc_write(port, MT6370_REG_IDLE_CTRL, + MT6370_REG_IDLE_SET(0, 1, 0, 0)); + /* CC Detect Debounce 5 */ + rv |= tcpc_write(port, MT6370_REG_TTCPC_FILTER, 5); + /* DRP Duty */ + rv |= tcpc_write(port, MT6370_REG_DRP_TOGGLE_CYCLE, 4); + rv |= tcpc_write16(port, MT6370_REG_DRP_DUTY_CTRL, 400); + /* Vconn OC on */ + rv |= tcpc_write(port, MT6370_REG_VCONN_CLIMITEN, 1); + /* PHY control */ + rv |= tcpc_write(port, MT6370_REG_PHY_CTRL1, + MT6370_REG_PHY_CTRL1_SET(0, 7, 0, 1)); + rv |= tcpc_write(port, MT6370_REG_PHY_CTRL3, 0x82); + + return rv; +} + +#ifndef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +static int mt6370_get_cc(int port, int *cc1, int *cc2) +{ + int status; + int rv; + int role; + + rv = tcpc_read(port, TCPC_REG_CC_STATUS, &status); + + /* If tcpc read fails, return error and CC as open */ + if (rv) { + *cc1 = TYPEC_CC_VOLT_OPEN; + *cc2 = TYPEC_CC_VOLT_OPEN; + return rv; + } + + *cc1 = TCPC_REG_CC_STATUS_CC1(status); + *cc2 = TCPC_REG_CC_STATUS_CC2(status); + + /* + * If status is not open, then OR in termination to convert to + * enum tcpc_cc_voltage_status. + * + * MT6370 TCPC follows USB PD 1.0 protocol. When DRP not auto-toggling, + * it will not update the DRP_RESULT bits in TCPC_REG_CC_STATUS, + * instead, we should check CC1/CC2 bits in TCPC_REG_ROLE_CTRL. + */ + rv = tcpc_read(port, TCPC_REG_ROLE_CTRL, &role); + + if (*cc1 != TYPEC_CC_VOLT_OPEN) + *cc1 |= (TCPC_REG_ROLE_CTRL_CC1(role) == TYPEC_CC_RD) << 2; + if (*cc2 != TYPEC_CC_VOLT_OPEN) + *cc2 |= (TCPC_REG_ROLE_CTRL_CC2(role) == TYPEC_CC_RD) << 2; + + return rv; +} +#endif + +/* MT6370 is a TCPCI compatible port controller */ +const struct tcpm_drv mt6370_tcpm_drv = { + .init = &mt6370_init, + .release = &tcpci_tcpm_release, +#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE + .get_cc = &tcpci_tcpm_get_cc, +#else + .get_cc = &mt6370_get_cc, +#endif +#ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC + .get_vbus_level = &tcpci_tcpm_get_vbus_level, +#endif + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message = &tcpci_tcpm_get_message, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, +#ifdef CONFIG_USB_PD_DISCHARGE_TCPC + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, +#endif +#ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE + .drp_toggle = &tcpci_tcpc_drp_toggle, +#endif + .get_chip_info = &tcpci_get_chip_info, +#ifdef CONFIG_USBC_PPC + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, +#endif +}; diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h new file mode 100644 index 0000000000..ff9ac569ee --- /dev/null +++ b/driver/tcpm/mt6370.h @@ -0,0 +1,179 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * MT6370 TCPC Driver + */ + +#ifndef __CROS_EC_USB_PD_TCPM_MT6370_H +#define __CROS_EC_USB_PD_TCPM_MT6370_H + +/* MT6370 Private RegMap */ + +#define MT6370_REG_PHY_CTRL1 0x80 +#define MT6370_REG_PHY_CTRL2 0x81 +#define MT6370_REG_PHY_CTRL3 0x82 +#define MT6370_REG_PHY_CTRL6 0x85 + +#define MT6370_REG_CLK_CTRL2 0x87 +#define MT6370_REG_CLK_CTRL3 0x88 + +#define MT6370_REG_RUST_STATUS 0x8A +#define MT6370_REG_RUST_INT_EVENT 0x8B +#define MT6370_REG_RUST_MASK 0x8C +#define MT6370_REG_BMC_CTRL 0x90 +#define MT6370_REG_BMCIO_RXDZSEL 0x93 +#define MT6370_REG_VCONN_CLIMITEN 0x95 + +#define MT6370_REG_OVP_FLAG_SEL 0x96 + +#define MT6370_REG_RT_STATUS 0x97 +#define MT6370_REG_RT_INT 0x98 +#define MT6370_REG_RT_MASK 0x99 +#define RT5081_REG_BMCIO_RXDZEN 0x9A +#define MT6370_REG_IDLE_CTRL 0x9B +#define MT6370_REG_INTRST_CTRL 0x9C +#define MT6370_REG_WATCHDOG_CTRL 0x9D +#define MT6370_REG_I2CRST_CTRL 0X9E + +#define MT6370_REG_SWRESET 0xA0 +#define MT6370_REG_TTCPC_FILTER 0xA1 +#define MT6370_REG_DRP_TOGGLE_CYCLE 0xA2 +#define MT6370_REG_DRP_DUTY_CTRL 0xA3 +#define MT6370_REG_RUST_DETECTION 0xAD +#define MT6370_REG_RUST_CONTROL 0xAE +#define MT6370_REG_BMCIO_RXDZEN 0xAF +#define MT6370_REG_DRP_RUST 0xB9 + +#define MT6370_REG_UNLOCK_PW2 0xF0 +#define MT6370_REG_UNLOCK_PW1 0xF1 + +#define MT6370_TCPC_I2C_ADDR 0x9C + +/* + * MT6370_REG_PHY_CTRL1 0x80 + */ + +#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt, \ + rx_filter) \ + ((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) | \ + (rx_filter & 0x03)) + +/* + * MT6370_REG_CLK_CTRL2 0x87 + */ + +#define MT6370_REG_CLK_DIV_600K_EN (1 << 7) +#define MT6370_REG_CLK_BCLK2_EN (1 << 6) +#define MT6370_REG_CLK_BCLK2_TG_EN (1 << 5) +#define MT6370_REG_CLK_DIV_300K_EN (1 << 3) +#define MT6370_REG_CLK_CK_300K_EN (1 << 2) +#define MT6370_REG_CLK_BCLK_EN (1 << 1) +#define MT6370_REG_CLK_BCLK_TH_EN (1 << 0) + +/* + * MT6370_REG_CLK_CTRL3 0x88 + */ + +#define MT6370_REG_CLK_OSCMUX_RG_EN (1 << 7) +#define MT6370_REG_CLK_CK_24M_EN (1 << 6) +#define MT6370_REG_CLK_OSC_RG_EN (1 << 5) +#define MT6370_REG_CLK_DIV_2P4M_EN (1 << 4) +#define MT6370_REG_CLK_CK_2P4M_EN (1 << 3) +#define MT6370_REG_CLK_PCLK_EN (1 << 2) +#define MT6370_REG_CLK_PCLK_RG_EN (1 << 1) +#define MT6370_REG_CLK_PCLK_TG_EN (1 << 0) + +/* + * MT6370_REG_RX_TX_DBG 0x8b + */ + +#define MT6370_REG_RX_TX_DBG_RX_BUSY (1 << 7) +#define MT6370_REG_RX_TX_DBG_TX_BUSY (1 << 6) + +/* + * MT6370_REG_BMC_CTRL 0x90 + */ + +#define MT6370_REG_IDLE_EN (1 << 6) +#define MT6370_REG_DISCHARGE_EN (1 << 5) +#define MT6370_REG_BMCIO_LPRPRD (1 << 4) +#define MT6370_REG_BMCIO_LPEN (1 << 3) +#define MT6370_REG_BMCIO_BG_EN (1 << 2) +#define MT6370_REG_VBUS_DET_EN (1 << 1) +#define MT6370_REG_BMCIO_OSC_EN (1 << 0) + +/* + * MT6370_REG_RT_STATUS 0x97 + */ + +#define MT6370_REG_RA_DETACH (1 << 5) +#define MT6370_REG_VBUS_80 (1 << 1) + +/* + * MT6370_REG_RT_INT 0x98 + */ + +#define MT6370_REG_INT_RA_DETACH (1 << 5) +#define MT6370_REG_INT_WATCHDOG (1 << 2) +#define MT6370_REG_INT_VBUS_80 (1 << 1) +#define MT6370_REG_INT_WAKEUP (1 << 0) + +/* + * MT6370_REG_RT_MASK 0x99 + */ + +#define MT6370_REG_M_RA_DETACH (1 << 5) +#define MT6370_REG_M_WATCHDOG (1 << 2) +#define MT6370_REG_M_VBUS_80 (1 << 1) +#define MT6370_REG_M_WAKEUP (1 << 0) + +/* + * MT6370_REG_IDLE_CTRL 0x9B + */ + +#define MT6370_REG_CK_300K_SEL (1 << 7) +#define MT6370_REG_SHIPPING_OFF (1 << 5) +#define MT6370_REG_ENEXTMSG (1 << 4) +#define MT6370_REG_AUTOIDLE_EN (1 << 3) + +/* timeout = (tout*2+1) * 6.4ms */ +#ifdef CONFIG_USB_PD_REV30 +#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ + ((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) | \ + MT6370_REG_ENEXTMSG) +#else +#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ + ((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07)) +#endif + +/* + * MT6370_REG_INTRST_CTRL 0x9C + */ + +#define MT6370_REG_INTRST_EN (1 << 7) + +/* timeout = (tout+1) * 0.2sec */ +#define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03)) + +/* + * MT6370_REG_WATCHDOG_CTRL 0x9D + */ + +#define MT6370_REG_WATCHDOG_EN (1 << 7) + +/* timeout = (tout+1) * 0.4sec */ +#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07)) + +/* + * MT6370_REG_I2CRST_CTRL 0x9E + */ + +#define MT6370_REG_I2CRST_EN (1 << 7) + +/* timeout = (tout+1) * 12.5ms */ +#define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f)) + +extern const struct tcpm_drv mt6370_tcpm_drv; + +#endif /* __CROS_EC_USB_PD_TCPM_MT6370_H */ diff --git a/include/config.h b/include/config.h index 64dbf8c9ea..f2dd9496b6 100644 --- a/include/config.h +++ b/include/config.h @@ -3113,6 +3113,7 @@ #undef CONFIG_USB_PD_TCPM_ANX7688 #undef CONFIG_USB_PD_TCPM_PS8751 #undef CONFIG_USB_PD_TCPM_PS8805 +#undef CONFIG_USB_PD_TCPM_MT6370 /* * Adds an EC console command to erase the ANX7447 OCM flash. |