zephyr: remove duplicated structure for npcx SHI driver

Revert "dts: Remove upstream SHI driver in favor of our own"

This reverts commit 9a9669c83100f8833d066e8a0e58a561075c3e9f and
removes the duplicates structure and defines that can now be
used from the upstream Zephyr header files.

BRANCH=main
BUG=b:265763662
TEST=run the host commands test on affected boards
LOW_COVERAGE_REASON=No tests are available for EC on-chip peripherals.

Change-Id: Ibc26beae8476bf3cdd5cc83ccaa5b66ead99dc41
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4180587
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: Michał Barnaś <barnas@google.com>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Michał Barnaś <barnas@google.com>

2 files changed, 27 insertions, 112 deletions

diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c
index 48513244b6..39485ecced 100644
--- a/zephyr/drivers/cros_shi/cros_shi_npcx.c
+++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c
@@ -175,13 +175,13 @@ struct cros_shi_npcx_data {
 /* Driver convenience defines */
 #define DRV_CONFIG(dev) ((const struct cros_shi_npcx_config *)(dev)->config)
 #define DRV_DATA(dev) ((struct cros_shi_npcx_data *)(dev)->data)
-#define HAL_INSTANCE(dev) (struct cros_shi_reg *)(DRV_CONFIG(dev)->base)
+#define HAL_INSTANCE(dev) (struct shi_reg *)(DRV_CONFIG(dev)->base)
 
 /* Forward declaration */
-static void cros_shi_npcx_reset_prepare(struct cros_shi_reg *const inst);
+static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst);
 
 /* Read pointer of input or output buffer by consecutive reading */
-static uint32_t shi_read_buf_pointer(struct cros_shi_reg *const inst)
+static uint32_t shi_read_buf_pointer(struct shi_reg *const inst)
 {
 	uint8_t stat;
 
@@ -197,7 +197,7 @@ static uint32_t shi_read_buf_pointer(struct cros_shi_reg *const inst)
  * Valid offset of SHI output buffer to write.
  * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
  */
-static uint32_t shi_valid_obuf_offset(struct cros_shi_reg *const inst)
+static uint32_t shi_valid_obuf_offset(struct shi_reg *const inst)
 {
 	return (shi_read_buf_pointer(inst) + SHI_OUT_PREAMBLE_LENGTH) %
 	       SHI_OBUF_FULL_SIZE;
@@ -228,8 +228,7 @@ static void shi_write_half_outbuf(void)
  * This routine read SHI input buffer to msg buffer until
  * we have received a certain number of bytes
  */
-static int shi_read_inbuf_wait(struct cros_shi_reg *const inst,
-			       uint32_t szbytes)
+static int shi_read_inbuf_wait(struct shi_reg *const inst, uint32_t szbytes)
 {
 	/* Copy data to msg buffer from input buffer */
 	for (uint32_t i = 0; i < szbytes; i++, shi_params.sz_received++) {
@@ -250,7 +249,7 @@ static int shi_read_inbuf_wait(struct cros_shi_reg *const inst,
 }
 
 /* This routine fills out all SHI output buffer with status byte */
-static void shi_fill_out_status(struct cros_shi_reg *const inst, uint8_t status)
+static void shi_fill_out_status(struct shi_reg *const inst, uint8_t status)
 {
 	uint8_t start, end;
 	volatile uint8_t *fill_ptr;
@@ -288,7 +287,7 @@ static void shi_fill_out_status(struct cros_shi_reg *const inst, uint8_t status)
 }
 
 /* This routine handles shi received unexpected data */
-static void shi_bad_received_data(struct cros_shi_reg *const inst)
+static void shi_bad_received_data(struct shi_reg *const inst)
 {
 	/* State machine mismatch, timeout, or protocol we can't handle. */
 	shi_fill_out_status(inst, EC_SPI_RX_BAD_DATA);
@@ -310,7 +309,7 @@ static void shi_bad_received_data(struct cros_shi_reg *const inst)
  * This routine write SHI output buffer from msg buffer over halt of it.
  * It make sure we have enough time to handle next operations.
  */
-static void shi_write_first_pkg_outbuf(struct cros_shi_reg *const inst,
+static void shi_write_first_pkg_outbuf(struct shi_reg *const inst,
 				       uint16_t szbytes)
 {
 	uint8_t size, offset;
@@ -359,8 +358,7 @@ static void shi_write_first_pkg_outbuf(struct cros_shi_reg *const inst,
  */
 static void shi_send_response_packet(struct host_packet *pkt)
 {
-	struct cros_shi_reg *const inst =
-		(struct cros_shi_reg *)(cros_shi_cfg.base);
+	struct shi_reg *const inst = (struct shi_reg *)(cros_shi_cfg.base);
 
 	/*
 	 * Disable interrupts. This routine is not called from interrupt
@@ -399,7 +397,7 @@ static void shi_send_response_packet(struct host_packet *pkt)
 	__enable_irq();
 }
 
-void shi_handle_host_package(struct cros_shi_reg *const inst)
+void shi_handle_host_package(struct shi_reg *const inst)
 {
 	uint32_t sz_inbuf_int = shi_params.sz_request / SHI_IBUF_HALF_SIZE;
 	uint32_t cnt_inbuf_int = shi_params.sz_received / SHI_IBUF_HALF_SIZE;
@@ -441,7 +439,7 @@ void shi_handle_host_package(struct cros_shi_reg *const inst)
 	host_packet_receive(&shi_packet);
 }
 
-static void shi_parse_header(struct cros_shi_reg *const inst)
+static void shi_parse_header(struct shi_reg *const inst)
 {
 	/* We're now inside a transaction */
 	state = SHI_STATE_RECEIVING;
@@ -484,7 +482,7 @@ static void shi_parse_header(struct cros_shi_reg *const inst)
 	}
 }
 
-static void shi_sec_ibf_int_enable(struct cros_shi_reg *const inst, int enable)
+static void shi_sec_ibf_int_enable(struct shi_reg *const inst, int enable)
 {
 	if (enable) {
 		/* Setup IBUFLVL2 threshold and enable it */
@@ -531,7 +529,7 @@ static void log_unexpected_state(char *isr_name)
 	last_error_state = state;
 }
 
-static void shi_handle_cs_assert(struct cros_shi_reg *const inst)
+static void shi_handle_cs_assert(struct shi_reg *const inst)
 {
 	/* If not enabled, ignore glitches on SHI_CS_L */
 	if (state == SHI_STATE_DISABLED)
@@ -560,7 +558,7 @@ static void shi_handle_cs_assert(struct cros_shi_reg *const inst)
 	disable_sleep(SLEEP_MASK_SPI);
 }
 
-static void shi_handle_cs_deassert(struct cros_shi_reg *const inst)
+static void shi_handle_cs_deassert(struct shi_reg *const inst)
 {
 	/*
 	 * If the buffer is still used by the host command.
@@ -598,7 +596,7 @@ static void shi_handle_cs_deassert(struct cros_shi_reg *const inst)
 	DEBUG_CPRINTF("END\n");
 }
 
-static void shi_handle_input_buf_half_full(struct cros_shi_reg *const inst)
+static void shi_handle_input_buf_half_full(struct shi_reg *const inst)
 {
 	if (state == SHI_STATE_RECEIVING) {
 		/* Read data from input to msg buffer */
@@ -620,7 +618,7 @@ static void shi_handle_input_buf_half_full(struct cros_shi_reg *const inst)
 	}
 }
 
-static void shi_handle_input_buf_full(struct cros_shi_reg *const inst)
+static void shi_handle_input_buf_full(struct shi_reg *const inst)
 {
 	if (state == SHI_STATE_RECEIVING) {
 		/* read data from input to msg buffer */
@@ -646,7 +644,7 @@ static void cros_shi_npcx_isr(const struct device *dev)
 {
 	uint8_t stat;
 	uint8_t stat2;
-	struct cros_shi_reg *const inst = HAL_INSTANCE(dev);
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Read status register and clear interrupt status early */
 	stat = inst->EVSTAT;
@@ -719,7 +717,7 @@ static void cros_shi_npcx_isr(const struct device *dev)
 	}
 }
 
-static void cros_shi_npcx_reset_prepare(struct cros_shi_reg *const inst)
+static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst)
 {
 	uint32_t i;
 
@@ -768,7 +766,7 @@ static int cros_shi_npcx_enable(const struct device *dev)
 {
 	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
 	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
-	struct cros_shi_reg *const inst = HAL_INSTANCE(dev);
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
 	int ret;
 
 	ret = clock_control_on(clk_dev,
@@ -833,7 +831,7 @@ static int shi_npcx_init(const struct device *dev)
 {
 	int ret;
 	const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev);
-	struct cros_shi_reg *const inst = HAL_INSTANCE(dev);
+	struct shi_reg *const inst = HAL_INSTANCE(dev);
 	const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
 
 	/* Turn on shi device clock first */
@@ -920,10 +918,10 @@ DEVICE_DT_INST_DEFINE(0, shi_npcx_init, /* pm_control_fn= */ NULL,
 		      &cros_shi_npcx_driver_api);
 
 /* KBS register structure check */
-NPCX_REG_SIZE_CHECK(cros_shi_reg, 0x120);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, SHICFG1, 0x001);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, EVENABLE, 0x005);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, IBUFSTAT, 0x00a);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, EVENABLE2, 0x010);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, OBUF, 0x020);
-NPCX_REG_OFFSET_CHECK(cros_shi_reg, IBUF, 0x0A0);
+NPCX_REG_SIZE_CHECK(shi_reg, 0x120);
+NPCX_REG_OFFSET_CHECK(shi_reg, SHICFG1, 0x001);
+NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE, 0x005);
+NPCX_REG_OFFSET_CHECK(shi_reg, IBUFSTAT, 0x00a);
+NPCX_REG_OFFSET_CHECK(shi_reg, EVENABLE2, 0x010);
+NPCX_REG_OFFSET_CHECK(shi_reg, OBUF, 0x020);
+NPCX_REG_OFFSET_CHECK(shi_reg, IBUF, 0x0A0);
diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
index ef3051e3de..16012c083e 100644
--- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
+++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
@@ -25,87 +25,4 @@ struct mtc_reg {
 #define NPCX_WTC_PTO 30
 #define NPCX_WTC_WIE 31
 
-/* SHI (Serial Host Interface) registers */
-struct cros_shi_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: SHI Configuration 1 */
-	volatile uint8_t SHICFG1;
-	/* 0x002: SHI Configuration 2 */
-	volatile uint8_t SHICFG2;
-	volatile uint8_t reserved2[2];
-	/* 0x005: Event Enable */
-	volatile uint8_t EVENABLE;
-	/* 0x006: Event Status */
-	volatile uint8_t EVSTAT;
-	/* 0x007: SHI Capabilities */
-	volatile uint8_t CAPABILITY;
-	/* 0x008: Status */
-	volatile uint8_t STATUS;
-	volatile uint8_t reserved3;
-	/* 0x00A: Input Buffer Status */
-	volatile uint8_t IBUFSTAT;
-	/* 0x00B: Output Buffer Status */
-	volatile uint8_t OBUFSTAT;
-	/* 0x00C: SHI Configuration 3 */
-	volatile uint8_t SHICFG3;
-	/* 0x00D: SHI Configuration 4 */
-	volatile uint8_t SHICFG4;
-	/* 0x00E: SHI Configuration 5 */
-	volatile uint8_t SHICFG5;
-	/* 0x00F: Event Status 2 */
-	volatile uint8_t EVSTAT2;
-	/* 0x010: Event Enable 2 */
-	volatile uint8_t EVENABLE2;
-	volatile uint8_t reserved4[15];
-	/* 0x20~0x9F: Output Buffer */
-	volatile uint8_t OBUF[128];
-	/* 0xA0~0x11F: Input Buffer */
-	volatile uint8_t IBUF[128];
-};
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN 0
-#define NPCX_SHICFG1_MODE 1
-#define NPCX_SHICFG1_WEN 2
-#define NPCX_SHICFG1_AUTIBF 3
-#define NPCX_SHICFG1_AUTOBE 4
-#define NPCX_SHICFG1_DAS 5
-#define NPCX_SHICFG1_CPOL 6
-#define NPCX_SHICFG1_IWRAP 7
-#define NPCX_SHICFG2_SIMUL 0
-#define NPCX_SHICFG2_BUSY 1
-#define NPCX_SHICFG2_ONESHOT 2
-#define NPCX_SHICFG2_SLWU 3
-#define NPCX_SHICFG2_REEN 4
-#define NPCX_SHICFG2_RESTART 5
-#define NPCX_SHICFG2_REEVEN 6
-#define NPCX_EVENABLE_OBEEN 0
-#define NPCX_EVENABLE_OBHEEN 1
-#define NPCX_EVENABLE_IBFEN 2
-#define NPCX_EVENABLE_IBHFEN 3
-#define NPCX_EVENABLE_EOREN 4
-#define NPCX_EVENABLE_EOWEN 5
-#define NPCX_EVENABLE_STSREN 6
-#define NPCX_EVENABLE_IBOREN 7
-#define NPCX_EVSTAT_OBE 0
-#define NPCX_EVSTAT_OBHE 1
-#define NPCX_EVSTAT_IBF 2
-#define NPCX_EVSTAT_IBHF 3
-#define NPCX_EVSTAT_EOR 4
-#define NPCX_EVSTAT_EOW 5
-#define NPCX_EVSTAT_STSR 6
-#define NPCX_EVSTAT_IBOR 7
-#define NPCX_STATUS_OBES 6
-#define NPCX_STATUS_IBFS 7
-#define NPCX_SHICFG3_OBUFLVLDIS 7
-#define NPCX_SHICFG4_IBUFLVLDIS 7
-#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS 7
-#define NPCX_EVSTAT2_IBHF2 0
-#define NPCX_EVSTAT2_CSNRE 1
-#define NPCX_EVSTAT2_CSNFE 2
-#define NPCX_EVENABLE2_IBHF2EN 0
-#define NPCX_EVENABLE2_CSNREEN 1
-#define NPCX_EVENABLE2_CSNFEEN 2
-
 #endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */