stm32f09x: fix flash protection offset

STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB),
which doesn't fit the layout requirement in config_std_internal_flash.h.
This CL hardcodes the layout and flash bank mapping.

BUG=chrome-os-partner:62372
BUG=chromium:694972
TEST=load on elm and manually enable write protect using flashrom
       # flashrom -p ec:dev=0 --wp-enable
     check ec console write protect option bytes, bank 31 is writable
       > rw 0x1ffff808
         read 0x1ffff808 = 0xff00ff00
       > rw 0x1ffff80c
         read 0x1ffff80c = 0x7f80ff00
BRANCH=oak

Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446800
Reviewed-by: Shawn N <shawnn@chromium.org>

5 files changed, 116 insertions, 1 deletions

diff --git a/board/elm/board.h b/board/elm/board.h
index 5dfd061f6f..6f5e56cb18 100644
--- a/board/elm/board.h
+++ b/board/elm/board.h
@@ -128,6 +128,30 @@
 #define CONFIG_CMD_I2C_PROTECT
 #define CONFIG_CMD_PD_CONTROL
 
+/*
+ * Flash layout:
+ *                            PSTATE(4KB)
+ *                              |
+ *          (124KB)             v            (132KB)
+ * |<-----Protected Region------>|<------Unprotected Region----->|
+ * |<--------RO image--------->| | |<--------RW image----------->|
+ * 0        (120KB)            ^ ^           (128KB)
+ *                             | |
+ *                             | sector 31(132KB sector)
+ *                             |
+ *                             sector 30(4KB sector)
+ */
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_SIZE
+#define CONFIG_RW_MEM_OFF                (128 * 1024)
+#define CONFIG_RW_SIZE                   (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF   (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (128 * 1024)
+#define CONFIG_WP_STORAGE_SIZE           (128 * 1024)
+
 /* Drivers */
 #ifndef __ASSEMBLER__
 
diff --git a/board/oak/board.h b/board/oak/board.h
index da022f48f0..d1a773c874 100644
--- a/board/oak/board.h
+++ b/board/oak/board.h
@@ -137,6 +137,30 @@
 #define CONFIG_USB_SWITCH_PI3USB9281
 #define CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT 2
 
+/*
+ * Flash layout:
+ *                            PSTATE(4KB)
+ *                              |
+ *          (124KB)             v            (132KB)
+ * |<-----Protected Region------>|<------Unprotected Region----->|
+ * |<--------RO image--------->| | |<--------RW image----------->|
+ * 0        (120KB)            ^ ^           (128KB)
+ *                             | |
+ *                             | sector 31(132KB sector)
+ *                             |
+ *                             sector 30(4KB sector)
+ */
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_SIZE
+#define CONFIG_RW_MEM_OFF                (128 * 1024)
+#define CONFIG_RW_SIZE                   (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF   (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (128 * 1024)
+#define CONFIG_WP_STORAGE_SIZE           (128 * 1024)
+
 #ifndef __ASSEMBLER__
 
 /* 48 MHz SYSCLK clock frequency */
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
index cfd57e1bf9..3da8a342f2 100644
--- a/chip/stm32/config-stm32f09x.h
+++ b/chip/stm32/config-stm32f09x.h
@@ -4,8 +4,12 @@
  */
 
 /* Memory mapping */
+/*
+ * Flash physical size: 256KB
+ * Write protect sectors: 31 4KB sectors, one 132KB sector
+ */
 #define CONFIG_FLASH_SIZE 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x2000
+#define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
 
@@ -17,3 +21,56 @@
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
+
+/*
+ * STM32F09x flash layout:
+ * - RO image starts at the beginning of flash: sector 0 ~ 29
+ * - PSTATE immediately follows the RO image: sector 30
+ * - RW image starts at 0x1f00: sector 31
+ * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30
+ * - Unprotected region consists of second half of RW image
+ *
+ *                            PSTATE(4KB)
+ *                              |
+ *          (124KB)             v            (132KB)
+ * |<-----Protected Region------>|<------Unprotected Region----->|
+ * |<--------RO image--------->| |<----------RW image----------->|
+ * 0        (120KB)            ^ ^
+ *                             | |
+ *                             | 31(132KB sector)
+ *                             |
+ *                             30
+ *
+ */
+
+#define _SECTOR_4KB             (4 * 1024)
+#define _SECTOR_132KB           (132 * 1024)
+
+/* The EC uses one sector to emulate persistent state */
+#define CONFIG_FLASH_PSTATE
+#define CONFIG_FW_PSTATE_SIZE   _SECTOR_4KB
+#define CONFIG_FW_PSTATE_OFF    (30 * _SECTOR_4KB)
+
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_STORAGE_OFF   0
+#define CONFIG_RO_SIZE          (30 * _SECTOR_4KB)
+#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
+				 CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RW_SIZE          _SECTOR_132KB
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE - \
+					  CONFIG_EC_WRITABLE_STORAGE_OFF)
+
+#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/* We map each write protect sector to a bank */
+#define PHYSICAL_BANKS          32
+#define WP_BANK_COUNT           31
+#define PSTATE_BANK             30
+#define PSTATE_BANK_COUNT       1
+
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 04041828af..159c660366 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -56,8 +56,10 @@
 /* Program is run directly from storage */
 #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
 
+#if !defined(CHIP_VARIANT_STM32F09X)
 /* Compute the rest of the flash params from these */
 #include "config_std_internal_flash.h"
+#endif
 
 /* System stack size */
 #if defined(CHIP_VARIANT_STM32F05X)
diff --git a/include/flash.h b/include/flash.h
index 03a6e89c25..b5699060d0 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -12,16 +12,24 @@
 #include "ec_commands.h"  /* For EC_FLASH_PROTECT_* flags */
 
 /* Number of physical flash banks */
+#ifndef PHYSICAL_BANKS
 #define PHYSICAL_BANKS (CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif
 
 /*WP region offset and size in units of flash banks */
 #define WP_BANK_OFFSET	(CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE)
+#ifndef WP_BANK_COUNT
 #define WP_BANK_COUNT	(CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif
 
 /* Persistent protection state flash offset / size / bank */
 #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)
+#ifndef PSTATE_BANK
 #define PSTATE_BANK	    (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE)
+#endif
+#ifndef PSTATE_BANK_COUNT
 #define PSTATE_BANK_COUNT   (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif
 #else
 #define PSTATE_BANK_COUNT	0
 #endif