diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 11:02:08 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-05-28 20:52:28 +0000 |
| commit | 4d38da5f607f10e283b5c6e635877ea75890bbff (patch) | |
| tree | d51821cb96e44cd828f5f730c0ceab558374328b | |
| parent | 61ec47022deba573cfade0fd7b07b9d4a0c6d66a (diff) | |
| download | chrome-ec-4d38da5f607f10e283b5c6e635877ea75890bbff.tar.gz | |
common: Add BIT macro
As requested for integration in kernel mfd subsystem, use BIT(...)
instead of (1 << ... ).
Add the macros, apply just to ec_commands.h for now.
BUG=None
BRANCH=None
TEST=Compile
Change-Id: I8509f1e8dc966799c3c4f0269b15f1ccc4138c07
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518658
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 8c6e95303832f7d445b415f1a1c0b0e34487ab2f)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1631301
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
Tested-by: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 1189 | ||||
| -rw-r--r-- | include/battery_smart.h | 76 | ||||
| -rw-r--r-- | include/compile_time_macros.h | 6 | ||||
| -rw-r--r-- | include/ec_commands.h | 255 |
4 files changed, 768 insertions, 758 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 9c41656e27..68a80516e2 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -9,6 +9,7 @@ #define __CROS_EC_REGISTERS_H #include "common.h" +#include "compile_time_macros.h" /* IRQ numbers */ #ifdef CHIP_FAMILY_STM32F0 @@ -462,70 +463,70 @@ defined(CHIP_FAMILY_STM32L4) || defined(CHIP_VARIANT_STM32F76X) || \ defined(CHIP_FAMILY_STM32H7) #define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE (1 << 0) -#define STM32_USART_CR1_UESM (1 << 1) -#define STM32_USART_CR1_RE (1 << 2) -#define STM32_USART_CR1_TE (1 << 3) -#define STM32_USART_CR1_RXNEIE (1 << 5) -#define STM32_USART_CR1_TCIE (1 << 6) -#define STM32_USART_CR1_TXEIE (1 << 7) -#define STM32_USART_CR1_PS (1 << 9) -#define STM32_USART_CR1_PCE (1 << 10) -#define STM32_USART_CR1_M (1 << 12) -#define STM32_USART_CR1_OVER8 (1 << 15) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) #define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP (1 << 15) +#define STM32_USART_CR2_SWAP BIT(15) #define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE (1 << 0) -#define STM32_USART_CR3_DMAR (1 << 6) -#define STM32_USART_CR3_DMAT (1 << 7) -#define STM32_USART_CR3_ONEBIT (1 << 11) -#define STM32_USART_CR3_OVRDIS (1 << 12) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE (1 << 22) +#define STM32_USART_CR3_WUFIE BIT(22) #define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) #define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) #define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) #define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) #define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) #define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF (1 << 3) -#define STM32_USART_ICR_TCCF (1 << 6) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) #define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) #define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) #define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ #define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE (1 << 3) -#define STM32_USART_SR_RXNE (1 << 5) -#define STM32_USART_SR_TC (1 << 6) -#define STM32_USART_SR_TXE (1 << 7) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 && !CHIP_FAMILY_STM32L4 */ #define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE (1 << 3) -#define STM32_USART_SR_RXNE (1 << 5) -#define STM32_USART_SR_TC (1 << 6) -#define STM32_USART_SR_TXE (1 << 7) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) #define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) #define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) #define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE (1 << 2) -#define STM32_USART_CR1_TE (1 << 3) -#define STM32_USART_CR1_RXNEIE (1 << 5) -#define STM32_USART_CR1_TCIE (1 << 6) -#define STM32_USART_CR1_TXEIE (1 << 7) -#define STM32_USART_CR1_PS (1 << 9) -#define STM32_USART_CR1_PCE (1 << 10) -#define STM32_USART_CR1_M (1 << 12) -#define STM32_USART_CR1_UE (1 << 13) -#define STM32_USART_CR1_OVER8 (1 << 15) /* STM32L only */ +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_UE BIT(13) +#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ #define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) #define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE (1 << 0) -#define STM32_USART_CR3_DMAR (1 << 6) -#define STM32_USART_CR3_DMAT (1 << 7) -#define STM32_USART_CR3_ONEBIT (1 << 11) /* STM32L only */ +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ #define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) /* register aliases */ #define STM32_USART_TDR(base) STM32_USART_DR(base) @@ -544,15 +545,15 @@ REG32(STM32_TIM_BASE(n) + (offset)) #define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN (1 << 0) +#define STM32_TIM_CR1_CEN BIT(0) #define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) #define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) #define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) #define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) #define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG (1 << 0) +#define STM32_TIM_EGR_UG BIT(0) #define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE (1 << 2) +#define STM32_TIM_CCMR1_OC1PE BIT(2) /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ #define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) #define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) @@ -566,7 +567,7 @@ #define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) #define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) #define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) -#define STM32_TIM_CCER_CC1E (1 << 0) +#define STM32_TIM_CCER_CC1E BIT(0) #define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) #define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) #define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) @@ -576,7 +577,7 @@ #define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) #define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) #define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE (1 << 15) +#define STM32_TIM_BDTR_MOE BIT(15) #define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) #define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) #define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) @@ -625,20 +626,20 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) #define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) #define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN (1 << 6) -#define STM32_LPTIM_INT_UP (1 << 5) -#define STM32_LPTIM_INT_ARROK (1 << 4) -#define STM32_LPTIM_INT_CMPOK (1 << 3) -#define STM32_LPTIM_INT_EXTTRIG (1 << 2) -#define STM32_LPTIM_INT_ARRM (1 << 1) -#define STM32_LPTIM_INT_CMPM (1 << 0) +#define STM32_LPTIM_INT_DOWN BIT(6) +#define STM32_LPTIM_INT_UP BIT(5) +#define STM32_LPTIM_INT_ARROK BIT(4) +#define STM32_LPTIM_INT_CMPOK BIT(3) +#define STM32_LPTIM_INT_EXTTRIG BIT(2) +#define STM32_LPTIM_INT_ARRM BIT(1) +#define STM32_LPTIM_INT_CMPM BIT(0) #define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) #define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE (1 << 4) -#define STM32_LPTIM_CR_COUNTRST (1 << 3) -#define STM32_LPTIM_CR_CNTSTRT (1 << 2) -#define STM32_LPTIM_CR_SNGSTRT (1 << 1) -#define STM32_LPTIM_CR_ENABLE (1 << 0) +#define STM32_LPTIM_CR_RSTARE BIT(4) +#define STM32_LPTIM_CR_COUNTRST BIT(3) +#define STM32_LPTIM_CR_CNTSTRT BIT(2) +#define STM32_LPTIM_CR_SNGSTRT BIT(1) +#define STM32_LPTIM_CR_ENABLE BIT(0) #define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) #define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) #define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) @@ -736,93 +737,93 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ || defined(CHIP_FAMILY_STM32L4) #define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE (1 << 0) -#define STM32_I2C_CR1_TXIE (1 << 1) -#define STM32_I2C_CR1_RXIE (1 << 2) -#define STM32_I2C_CR1_ADDRIE (1 << 3) -#define STM32_I2C_CR1_NACKIE (1 << 4) -#define STM32_I2C_CR1_STOPIE (1 << 5) -#define STM32_I2C_CR1_ERRIE (1 << 7) -#define STM32_I2C_CR1_WUPEN (1 << 18) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) #define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN (1 << 10) -#define STM32_I2C_CR2_START (1 << 13) -#define STM32_I2C_CR2_STOP (1 << 14) -#define STM32_I2C_CR2_NACK (1 << 15) -#define STM32_I2C_CR2_RELOAD (1 << 24) -#define STM32_I2C_CR2_AUTOEND (1 << 25) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) #define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) #define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) #define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) #define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) #define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE (1 << 0) -#define STM32_I2C_ISR_TXIS (1 << 1) -#define STM32_I2C_ISR_RXNE (1 << 2) -#define STM32_I2C_ISR_ADDR (1 << 3) -#define STM32_I2C_ISR_NACK (1 << 4) -#define STM32_I2C_ISR_STOP (1 << 5) -#define STM32_I2C_ISR_TC (1 << 6) -#define STM32_I2C_ISR_TCR (1 << 7) -#define STM32_I2C_ISR_BERR (1 << 8) -#define STM32_I2C_ISR_ARLO (1 << 9) -#define STM32_I2C_ISR_OVR (1 << 10) -#define STM32_I2C_ISR_PECERR (1 << 11) -#define STM32_I2C_ISR_TIMEOUT (1 << 12) -#define STM32_I2C_ISR_ALERT (1 << 13) -#define STM32_I2C_ISR_BUSY (1 << 15) -#define STM32_I2C_ISR_DIR (1 << 16) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) #define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) #define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF (1 << 3) -#define STM32_I2C_ICR_NACKCF (1 << 4) -#define STM32_I2C_ICR_STOPCF (1 << 5) -#define STM32_I2C_ICR_BERRCF (1 << 8) -#define STM32_I2C_ICR_ARLOCF (1 << 9) -#define STM32_I2C_ICR_OVRCF (1 << 10) -#define STM32_I2C_ICR_TIMEOUTCF (1 << 12) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) #define STM32_I2C_ICR_ALL 0x3F38 #define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) #define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) #define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ #define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE (1 << 0) -#define STM32_I2C_CR1_START (1 << 8) -#define STM32_I2C_CR1_STOP (1 << 9) -#define STM32_I2C_CR1_ACK (1 << 10) -#define STM32_I2C_CR1_POS (1 << 11) -#define STM32_I2C_CR1_SWRST (1 << 15) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) #define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN (1 << 8) -#define STM32_I2C_CR2_ITEVTEN (1 << 9) -#define STM32_I2C_CR2_ITBUFEN (1 << 10) -#define STM32_I2C_CR2_DMAEN (1 << 11) -#define STM32_I2C_CR2_LAST (1 << 12) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) #define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 (1 << 14) +#define STM32_I2C_OAR1_B14 BIT(14) #define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL (1 << 0) +#define STM32_I2C_OAR2_ENDUAL BIT(0) #define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) #define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB (1 << 0) -#define STM32_I2C_SR1_ADDR (1 << 1) -#define STM32_I2C_SR1_BTF (1 << 2) -#define STM32_I2C_SR1_STOPF (1 << 4) -#define STM32_I2C_SR1_RXNE (1 << 6) -#define STM32_I2C_SR1_TXE (1 << 7) -#define STM32_I2C_SR1_BERR (1 << 8) -#define STM32_I2C_SR1_ARLO (1 << 9) -#define STM32_I2C_SR1_AF (1 << 10) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) #define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY (1 << 1) -#define STM32_I2C_SR2_TRA (1 << 2) -#define STM32_I2C_SR2_DUALF (1 << 7) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) #define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY (1 << 14) -#define STM32_I2C_CCR_FM (1 << 15) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) #define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 && !CHIP_FAMILY_STM32L4 */ #endif @@ -831,18 +832,18 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #if defined(CHIP_FAMILY_STM32F4) #define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE (1 << 0) -#define FMPI2C_CR1_TXDMAEN (1 << 14) -#define FMPI2C_CR1_RXDMAEN (1 << 15) +#define FMPI2C_CR1_PE BIT(0) +#define FMPI2C_CR1_TXDMAEN BIT(14) +#define FMPI2C_CR1_RXDMAEN BIT(15) #define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN (1 << 10) +#define FMPI2C_CR2_RD_WRN BIT(10) #define FMPI2C_READ 1 #define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START (1 << 13) -#define FMPI2C_CR2_STOP (1 << 14) -#define FMPI2C_CR2_NACK (1 << 15) -#define FMPI2C_CR2_RELOAD (1 << 24) -#define FMPI2C_CR2_AUTOEND (1 << 25) +#define FMPI2C_CR2_START BIT(13) +#define FMPI2C_CR2_STOP BIT(14) +#define FMPI2C_CR2_NACK BIT(15) +#define FMPI2C_CR2_RELOAD BIT(24) +#define FMPI2C_CR2_AUTOEND BIT(25) #define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) #define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) #define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) @@ -859,15 +860,15 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) #define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE (1 << 0) -#define FMPI2C_ISR_TXIS (1 << 1) -#define FMPI2C_ISR_RXNE (1 << 2) -#define FMPI2C_ISR_ADDR (1 << 3) -#define FMPI2C_ISR_NACKF (1 << 4) -#define FMPI2C_ISR_STOPF (1 << 5) -#define FMPI2C_ISR_BERR (1 << 8) -#define FMPI2C_ISR_ARLO (1 << 9) -#define FMPI2C_ISR_BUSY (1 << 15) +#define FMPI2C_ISR_TXE BIT(0) +#define FMPI2C_ISR_TXIS BIT(1) +#define FMPI2C_ISR_RXNE BIT(2) +#define FMPI2C_ISR_ADDR BIT(3) +#define FMPI2C_ISR_NACKF BIT(4) +#define FMPI2C_ISR_STOPF BIT(5) +#define FMPI2C_ISR_BERR BIT(8) +#define FMPI2C_ISR_ARLO BIT(9) +#define FMPI2C_ISR_BUSY BIT(15) #define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) #define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) @@ -892,24 +893,24 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #ifdef CHIP_FAMILY_STM32H7 #define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) #define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_CR3_BYPASS (1 << 0) -#define STM32_PWR_CR3_LDOEN (1 << 1) -#define STM32_PWR_CR3_SCUEN (1 << 2) -#define STM32_PWR_CR3_VBE (1 << 8) -#define STM32_PWR_CR3_VBRS (1 << 9) -#define STM32_PWR_CR3_USB33DEN (1 << 24) -#define STM32_PWR_CR3_USBREGEN (1 << 25) -#define STM32_PWR_CR3_USB33RDY (1 << 26) +#define STM32_PWR_CR3_BYPASS BIT(0) +#define STM32_PWR_CR3_LDOEN BIT(1) +#define STM32_PWR_CR3_SCUEN BIT(2) +#define STM32_PWR_CR3_VBE BIT(8) +#define STM32_PWR_CR3_VBRS BIT(9) +#define STM32_PWR_CR3_USB33DEN BIT(24) +#define STM32_PWR_CR3_USBREGEN BIT(25) +#define STM32_PWR_CR3_USB33RDY BIT(26) #define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_CPUCR_PDDS_D1 (1 << 0) -#define STM32_PWR_CPUCR_PDDS_D2 (1 << 1) -#define STM32_PWR_CPUCR_PDDS_D3 (1 << 2) -#define STM32_PWR_CPUCR_STOPF (1 << 5) -#define STM32_PWR_CPUCR_SBF (1 << 6) -#define STM32_PWR_CPUCR_SBF_D1 (1 << 7) -#define STM32_PWR_CPUCR_SBF_D2 (1 << 8) -#define STM32_PWR_CPUCR_CSSF (1 << 9) -#define STM32_PWR_CPUCR_RUN_D3 (1 << 11) +#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) +#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) +#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) +#define STM32_PWR_CPUCR_STOPF BIT(5) +#define STM32_PWR_CPUCR_SBF BIT(6) +#define STM32_PWR_CPUCR_SBF_D1 BIT(7) +#define STM32_PWR_CPUCR_SBF_D2 BIT(8) +#define STM32_PWR_CPUCR_CSSF BIT(9) +#define STM32_PWR_CPUCR_RUN_D3 BIT(11) #define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) #define STM32_PWR_D3CR_VOS1 (3 << 14) #define STM32_PWR_D3CR_VOS2 (2 << 14) @@ -922,24 +923,24 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #endif /* CHIP_FAMILY_STM32H7 */ #endif #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) -#define STM32_PWR_CSR_EWUP1 (1 << 8) -#define STM32_PWR_CSR_EWUP2 (1 << 9) -#define STM32_PWR_CSR_EWUP3 (1 << 10) -#define STM32_PWR_CSR_EWUP4 (1 << 11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 (1 << 12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 (1 << 13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 (1 << 14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 (1 << 15) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP1 BIT(8) +#define STM32_PWR_CSR_EWUP2 BIT(9) +#define STM32_PWR_CSR_EWUP3 BIT(10) +#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ #endif #if defined(CHIP_FAMILY_STM32L) #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION (1 << 0) -#define STM32_RCC_CR_HSIRDY (1 << 1) -#define STM32_RCC_CR_MSION (1 << 8) -#define STM32_RCC_CR_MSIRDY (1 << 9) -#define STM32_RCC_CR_PLLON (1 << 24) -#define STM32_RCC_CR_PLLRDY (1 << 25) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_MSION BIT(8) +#define STM32_RCC_CR_MSIRDY BIT(9) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) #define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) @@ -962,21 +963,21 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) #define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_SYSCFGEN (1 << 0) +#define STM32_RCC_SYSCFGEN BIT(0) #define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_PWREN (1 << 28) +#define STM32_RCC_PWREN BIT(28) #define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) #define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) #define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_HB_DMA1 (1 << 24) -#define STM32_RCC_PB2_TIM9 (1 << 2) -#define STM32_RCC_PB2_TIM10 (1 << 3) -#define STM32_RCC_PB2_TIM11 (1 << 4) -#define STM32_RCC_PB1_USB (1 << 23) +#define STM32_RCC_HB_DMA1 BIT(24) +#define STM32_RCC_PB2_TIM9 BIT(2) +#define STM32_RCC_PB2_TIM10 BIT(3) +#define STM32_RCC_PB2_TIM11 BIT(4) +#define STM32_RCC_PB1_USB BIT(23) #define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) #define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) @@ -984,14 +985,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #elif defined(CHIP_FAMILY_STM32L4) #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_MSION (1 << 0) -#define STM32_RCC_CR_MSIRDY (1 << 1) -#define STM32_RCC_CR_HSION (1 << 8) -#define STM32_RCC_CR_HSIRDY (1 << 10) -#define STM32_RCC_CR_HSEON (1 << 16) -#define STM32_RCC_CR_HSERDY (1 << 17) -#define STM32_RCC_CR_PLLON (1 << 24) -#define STM32_RCC_CR_PLLRDY (1 << 25) +#define STM32_RCC_CR_MSION BIT(0) +#define STM32_RCC_CR_MSIRDY BIT(1) +#define STM32_RCC_CR_HSION BIT(8) +#define STM32_RCC_CR_HSIRDY BIT(10) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) #define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) @@ -1035,21 +1036,21 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) #define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB1ENR_DMA1EN (1 << 0) -#define STM32_RCC_AHB1ENR_DMA2EN (1 << 1) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) #define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) #define STM32_RCC_AHB2ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB2ENR_RNGEN (1 << 18) +#define STM32_RCC_AHB2ENR_RNGEN BIT(18) #define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_PWREN (1 << 28) +#define STM32_RCC_PWREN BIT(28) #define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB1ENR2_LPUART1EN (1 << 0) +#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_SYSCFGEN (1 << 0) +#define STM32_RCC_SYSCFGEN BIT(0) #define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) @@ -1083,9 +1084,9 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) #define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK (1 << STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK (1 << STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) +#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) /* Possible clock sources for each peripheral */ #define STM32_RCC_CCIPR_UART_PCLK 0 @@ -1129,24 +1130,24 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CRRCR_HSI48ON (1<<0) -#define STM32_RCC_CRRCR_HSI48RDY (1<<1) -#define STM32_RCC_CRRCR_HSI48CAL_MASK (0x1ff<<7) +#define STM32_RCC_CRRCR_HSI48ON BIT(0) +#define STM32_RCC_CRRCR_HSI48RDY BIT(1) +#define STM32_RCC_CRRCR_HSI48CAL_MASK (0x1ff << 7) -#define STM32_RCC_PB2_TIM1 (1 << 11) -#define STM32_RCC_PB2_TIM8 (1 << 13) +#define STM32_RCC_PB2_TIM1 BIT(11) +#define STM32_RCC_PB2_TIM8 BIT(13) #define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) #define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE (1 << 0) -#define STM32_CRS_CR_SYNCWARNIE (1 << 1) -#define STM32_CRS_CR_ERRIE (1 << 2) -#define STM32_CRS_CR_ESYNCIE (1 << 3) -#define STM32_CRS_CR_CEN (1 << 5) -#define STM32_CRS_CR_AUTOTRIMEN (1 << 6) -#define STM32_CRS_CR_SWSYNC (1 << 7) +#define STM32_CRS_CR_SYNCOKIE BIT(0) +#define STM32_CRS_CR_SYNCWARNIE BIT(1) +#define STM32_CRS_CR_ERRIE BIT(2) +#define STM32_CRS_CR_ESYNCIE BIT(3) +#define STM32_CRS_CR_CEN BIT(5) +#define STM32_CRS_CR_AUTOTRIMEN BIT(6) +#define STM32_CRS_CR_SWSYNC BIT(7) #define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) #define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ @@ -1154,24 +1155,24 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) #define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) #define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL (1 << 31) +#define STM32_CRS_CFGR_SYNCPOL BIT(31) #define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF (1 << 0) -#define STM32_CRS_ISR_SYNCWARNF (1 << 1) -#define STM32_CRS_ISR_ERRF (1 << 2) -#define STM32_CRS_ISR_ESYNCF (1 << 3) -#define STM32_CRS_ISR_SYNCERR (1 << 8) -#define STM32_CRS_ISR_SYNCMISS (1 << 9) -#define STM32_CRS_ISR_TRIMOVF (1 << 10) -#define STM32_CRS_ISR_FEDIR (1 << 15) +#define STM32_CRS_ISR_SYNCOKF BIT(0) +#define STM32_CRS_ISR_SYNCWARNF BIT(1) +#define STM32_CRS_ISR_ERRF BIT(2) +#define STM32_CRS_ISR_ESYNCF BIT(3) +#define STM32_CRS_ISR_SYNCERR BIT(8) +#define STM32_CRS_ISR_SYNCMISS BIT(9) +#define STM32_CRS_ISR_TRIMOVF BIT(10) +#define STM32_CRS_ISR_FEDIR BIT(15) #define STM32_CRS_ISR_FECAP (0xffff << 16) #define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC (1 << 0) -#define STM32_CRS_ICR_SYNCWARINC (1 << 1) -#define STM32_CRS_ICR_ERRC (1 << 2) -#define STM32_CRS_ICR_ESYNCC (1 << 3) +#define STM32_CRS_ICR_SYNCOKC BIT(0) +#define STM32_CRS_ICR_SYNCWARINC BIT(1) +#define STM32_CRS_ICR_ERRC BIT(2) +#define STM32_CRS_ICR_ESYNCC BIT(3) #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) #define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) @@ -1180,14 +1181,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) #define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN (1 << 9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN (1 << 17) -#define STM32_RCC_APB2ENR_TIM17EN (1 << 18) -#define STM32_RCC_DBGMCUEN (1 << 22) -#define STM32_RCC_SYSCFGEN (1 << 0) +#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ +#define STM32_RCC_APB2ENR_TIM16EN BIT(17) +#define STM32_RCC_APB2ENR_TIM17EN BIT(18) +#define STM32_RCC_DBGMCUEN BIT(22) +#define STM32_RCC_SYSCFGEN BIT(0) #define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN (1 << 28) +#define STM32_RCC_PWREN BIT(28) #define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) @@ -1197,22 +1198,22 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) #define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ -#define STM32_RCC_HB_DMA1 (1 << 0) +#define STM32_RCC_HB_DMA1 BIT(0) /* STM32F373 */ -#define STM32_RCC_HB_DMA2 (1 << 1) -#define STM32_RCC_PB2_TIM1 (1 << 11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 (1 << 16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 (1 << 17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 (1 << 18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 (1 << 19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD (1 << 11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE (1 << 13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 (1 << 6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 (1 << 7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 (1 << 8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 (1 << 9) /* STM32F373 */ -#define STM32_RCC_PB1_USB (1 << 23) -#define STM32_RCC_PB1_CRS (1 << 27) +#define STM32_RCC_HB_DMA2 BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ +#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ +#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ +#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ +#define STM32_RCC_PB1_USB BIT(23) +#define STM32_RCC_PB1_CRS BIT(27) #define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) #define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) @@ -1220,12 +1221,12 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #elif defined(CHIP_FAMILY_STM32F4) #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION (1 << 0) -#define STM32_RCC_CR_HSIRDY (1 << 1) -#define STM32_RCC_CR_HSEON (1 << 16) -#define STM32_RCC_CR_HSERDY (1 << 17) -#define STM32_RCC_CR_PLLON (1 << 24) -#define STM32_RCC_CR_PLLRDY (1 << 25) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #if defined(CHIP_VARIANT_STM32F446) /* Required or recommended clocks for stm32f446 */ @@ -1241,7 +1242,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY (1 << 0) +#define STM32_FLASH_ACR_LATENCY BIT(0) #elif defined(CHIP_VARIANT_STM32F412) /* Required or recommended clocks for stm32f412 */ @@ -1273,7 +1274,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY (1 << 0) +#define STM32_FLASH_ACR_LATENCY BIT(0) #elif defined(CHIP_VARIANT_STM32F76X) /* Required or recommended clocks for stm32f767/769 */ @@ -1307,7 +1308,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) #define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE (1 << 22) +#define PLLCFGR_PLLSRC_HSE BIT(22) /* USB OTG FS: Must equal 48MHz */ #define PLLCFGR_PLLQ_OFF 24 #define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) @@ -1341,7 +1342,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) #define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST (1 << 29) +#define RCC_AHB1RSTR_OTGHSRST BIT(29) #define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) #define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) @@ -1351,31 +1352,31 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) #define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN (1 << 18) -#define STM32_RCC_AHB1ENR_DMA1EN (1 << 21) -#define STM32_RCC_AHB1ENR_DMA2EN (1 << 22) +#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) /* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 (1 << 21) -#define STM32_RCC_HB1_DMA2 (1 << 22) -#define STM32_RCC_AHB1ENR_OTGHSEN (1 << 29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN (1 << 30) +#define STM32_RCC_HB1_DMA1 BIT(21) +#define STM32_RCC_HB1_DMA2 BIT(22) +#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) +#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) #define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_OTGFSEN (1 << 7) +#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) #define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) #define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN (1 << 28) -#define STM32_RCC_I2C1EN (1 << 21) -#define STM32_RCC_I2C2EN (1 << 22) -#define STM32_RCC_I2C3EN (1 << 23) -#define STM32_RCC_FMPI2C4EN (1 << 24) +#define STM32_RCC_PWREN BIT(28) +#define STM32_RCC_I2C1EN BIT(21) +#define STM32_RCC_I2C2EN BIT(22) +#define STM32_RCC_I2C3EN BIT(23) +#define STM32_RCC_FMPI2C4EN BIT(24) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN (1 << 8) /* STM32F4 */ +#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ -#define STM32_RCC_PB2_USART6 (1 << 5) -#define STM32_RCC_SYSCFGEN (1 << 14) +#define STM32_RCC_PB2_USART6 BIT(5) +#define STM32_RCC_SYSCFGEN BIT(14) #define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) #define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) @@ -1385,14 +1386,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION (1 << 0) -#define STM32_RCC_CSR_LSIRDY (1 << 1) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) -#define STM32_RCC_HB_DMA1 (1 << 24) -#define STM32_RCC_PB2_TIM9 (1 << 2) -#define STM32_RCC_PB2_TIM10 (1 << 3) -#define STM32_RCC_PB2_TIM11 (1 << 4) -#define STM32_RCC_PB1_USB (1 << 23) +#define STM32_RCC_HB_DMA1 BIT(24) +#define STM32_RCC_PB2_TIM9 BIT(2) +#define STM32_RCC_PB2_TIM10 BIT(3) +#define STM32_RCC_PB2_TIM11 BIT(4) +#define STM32_RCC_PB1_USB BIT(23) #define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) #define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) @@ -1437,9 +1438,9 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) #define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) #define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) -#define STM32_RCC_AHB2ENR_RNGEN (1 << 6) -#define STM32_RCC_AHB2ENR_HASHEN (1 << 5) -#define STM32_RCC_AHB2ENR_CRYPTEN (1 << 4) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_HASHEN BIT(5) +#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) #define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) #define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff #define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) @@ -1447,7 +1448,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) #define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) -#define STM32_RCC_SYSCFGEN (1 << 1) +#define STM32_RCC_SYSCFGEN BIT(1) #define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) #define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) #define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) @@ -1460,18 +1461,18 @@ typedef volatile struct timer_ctlr timer_ctlr_t; /* Aliases */ #define STM32_RCC_APB1ENR STM32_RCC_APB1LENR -#define STM32_RCC_CR_HSION (1 << 0) -#define STM32_RCC_CR_HSIRDY (1 << 2) -#define STM32_RCC_CR_CSION (1 << 7) -#define STM32_RCC_CR_CSIRDY (1 << 8) -#define STM32_RCC_CR_HSI48ON (1 << 12) -#define STM32_RCC_CR_HSI48RDY (1 << 13) -#define STM32_RCC_CR_PLL1ON (1 << 24) -#define STM32_RCC_CR_PLL1RDY (1 << 25) -#define STM32_RCC_CR_PLL2ON (1 << 26) -#define STM32_RCC_CR_PLL2RDY (1 << 27) -#define STM32_RCC_CR_PLL3ON (1 << 28) -#define STM32_RCC_CR_PLL3RDY (1 << 29) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(2) +#define STM32_RCC_CR_CSION BIT(7) +#define STM32_RCC_CR_CSIRDY BIT(8) +#define STM32_RCC_CR_HSI48ON BIT(12) +#define STM32_RCC_CR_HSI48RDY BIT(13) +#define STM32_RCC_CR_PLL1ON BIT(24) +#define STM32_RCC_CR_PLL1RDY BIT(25) +#define STM32_RCC_CR_PLL2ON BIT(26) +#define STM32_RCC_CR_PLL2RDY BIT(27) +#define STM32_RCC_CR_PLL3ON BIT(28) +#define STM32_RCC_CR_PLL3RDY BIT(29) #define STM32_RCC_CFGR_SW_HSI (0 << 0) #define STM32_RCC_CFGR_SW_CSI (1 << 0) #define STM32_RCC_CFGR_SW_HSE (2 << 0) @@ -1496,7 +1497,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) #define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) #define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (11 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) #define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) #define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) #define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) @@ -1505,16 +1506,16 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) #define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) #define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN (1 << 0) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) #define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM (1 << 1) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) #define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) #define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) #define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) #define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) -#define STM32_RCC_PLLCFG_DIVP1EN (1 << 16) -#define STM32_RCC_PLLCFG_DIVQ1EN (1 << 17) -#define STM32_RCC_PLLCFG_DIVR1EN (1 << 18) +#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) +#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) +#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) #define STM32_RCC_PLLDIV_DIVN(n) (((n) - 1) << 0) #define STM32_RCC_PLLDIV_DIVP(p) (((p) - 1) << 9) #define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) @@ -1559,40 +1560,40 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) #define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) #define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) -#define STM32_RCC_CSR_LSION (1 << 0) -#define STM32_RCC_CSR_LSIRDY (1 << 1) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) #define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) #define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) /* Peripheral bits for APB1ENR regs */ -#define STM32_RCC_PB1_LPTIM1 (1 << 9) +#define STM32_RCC_PB1_LPTIM1 BIT(9) /* Peripheral bits for APB2ENR regs */ -#define STM32_RCC_PB2_TIM1 (1 << 0) -#define STM32_RCC_PB2_TIM2 (1 << 1) -#define STM32_RCC_PB2_USART1 (1 << 4) -#define STM32_RCC_PB2_SPI1 (1 << 12) -#define STM32_RCC_PB2_SPI4 (1 << 13) -#define STM32_RCC_PB2_TIM15 (1 << 16) -#define STM32_RCC_PB2_TIM16 (1 << 17) -#define STM32_RCC_PB2_TIM17 (1 << 18) +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM2 BIT(1) +#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_SPI1 BIT(12) +#define STM32_RCC_PB2_SPI4 BIT(13) +#define STM32_RCC_PB2_TIM15 BIT(16) +#define STM32_RCC_PB2_TIM16 BIT(17) +#define STM32_RCC_PB2_TIM17 BIT(18) /* Peripheral bits for AHB1/2/3/4ENR regs */ -#define STM32_RCC_HB1_DMA1 (1 << 0) -#define STM32_RCC_HB1_DMA2 (1 << 1) -#define STM32_RCC_HB3_MDMA (1 << 0) -#define STM32_RCC_HB4_BDMA (1 << 21) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB3_MDMA BIT(0) +#define STM32_RCC_HB4_BDMA BIT(21) #else #error Unsupported chip variant #endif /* RTC domain control register */ -#define STM32_RCC_BDCR_BDRST (1 << 16) -#define STM32_RCC_BDCR_RTCEN (1 << 15) -#define STM32_RCC_BDCR_LSERDY (1 << 1) -#define STM32_RCC_BDCR_LSEON (1 << 0) +#define STM32_RCC_BDCR_BDRST BIT(16) +#define STM32_RCC_BDCR_RTCEN BIT(15) +#define STM32_RCC_BDCR_LSERDY BIT(1) +#define STM32_RCC_BDCR_LSEON BIT(0) #define BDCR_RTCSEL_MASK ((0x3) << 8) #define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) #define BDCR_SRC_LSE 0x1 @@ -1600,29 +1601,29 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define BDCR_SRC_HSE 0x3 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_TIM2 (1 << 0) -#define STM32_RCC_PB1_TIM3 (1 << 1) -#define STM32_RCC_PB1_TIM4 (1 << 2) -#define STM32_RCC_PB1_TIM5 (1 << 3) -#define STM32_RCC_PB1_TIM6 (1 << 4) -#define STM32_RCC_PB1_TIM7 (1 << 5) -#define STM32_RCC_PB1_TIM12 (1 << 6) /* STM32H7 */ -#define STM32_RCC_PB1_TIM13 (1 << 7) /* STM32H7 */ -#define STM32_RCC_PB1_TIM14 (1 << 8) /* STM32H7 */ -#define STM32_RCC_PB1_RTC (1 << 10) /* DBGMCU only */ -#define STM32_RCC_PB1_WWDG (1 << 11) -#define STM32_RCC_PB1_IWDG (1 << 12) /* DBGMCU only */ -#define STM32_RCC_PB1_SPI2 (1 << 14) -#define STM32_RCC_PB1_SPI3 (1 << 15) -#define STM32_RCC_PB1_USART2 (1 << 17) -#define STM32_RCC_PB1_USART3 (1 << 18) -#define STM32_RCC_PB1_USART4 (1 << 19) -#define STM32_RCC_PB1_USART5 (1 << 20) -#define STM32_RCC_PB2_SPI1 (1 << 12) +#define STM32_RCC_PB1_TIM2 BIT(0) +#define STM32_RCC_PB1_TIM3 BIT(1) +#define STM32_RCC_PB1_TIM4 BIT(2) +#define STM32_RCC_PB1_TIM5 BIT(3) +#define STM32_RCC_PB1_TIM6 BIT(4) +#define STM32_RCC_PB1_TIM7 BIT(5) +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ +#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ +#define STM32_RCC_PB1_WWDG BIT(11) +#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ +#define STM32_RCC_PB1_SPI2 BIT(14) +#define STM32_RCC_PB1_SPI3 BIT(15) +#define STM32_RCC_PB1_USART2 BIT(17) +#define STM32_RCC_PB1_USART3 BIT(18) +#define STM32_RCC_PB1_USART4 BIT(19) +#define STM32_RCC_PB1_USART5 BIT(20) +#define STM32_RCC_PB2_SPI1 BIT(12) #if defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) -#define STM32_RCC_PB2_USART1 (1 << 4) +#define STM32_RCC_PB2_USART1 BIT(4) #else -#define STM32_RCC_PB2_USART1 (1 << 14) +#define STM32_RCC_PB2_USART1 BIT(14) #endif /* Reset causes definitions */ @@ -1663,7 +1664,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) #define STM32_WWDG_TB_8 (3 << 7) -#define STM32_WWDG_EWI (1 << 9) +#define STM32_WWDG_EWI BIT(9) #define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) #define STM32_IWDG_KR_UNLOCK 0x5555 @@ -1673,9 +1674,9 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) #define STM32_IWDG_RLR_MAX 0x0fff #define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) -#define STM32_IWDG_SR_WVU (1 << 2) -#define STM32_IWDG_SR_RVU (1 << 1) -#define STM32_IWDG_SR_PVU (1 << 0) +#define STM32_IWDG_SR_WVU BIT(2) +#define STM32_IWDG_SR_RVU BIT(1) +#define STM32_IWDG_SR_PVU BIT(0) #define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) /* --- Real-Time Clock --- */ @@ -1686,15 +1687,15 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) #define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) #define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD (1 << 5) -#define STM32_RTC_CR_ALRAE (1 << 8) -#define STM32_RTC_CR_ALRAIE (1 << 12) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) #define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF (1 << 0) -#define STM32_RTC_ISR_RSF (1 << 5) -#define STM32_RTC_ISR_INITF (1 << 6) -#define STM32_RTC_ISR_INIT (1 << 7) -#define STM32_RTC_ISR_ALRAF (1 << 8) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) #define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) #define STM32_RTC_PRER_A_MASK (0x7f << 16) #define STM32_RTC_PRER_S_MASK (0x7fff << 0) @@ -1771,9 +1772,9 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) #ifdef CHIP_FAMILY_STM32H7 -#define STM32_SPI_CR1_SPE (1 << 0) -#define STM32_SPI_CR1_CSTART (1 << 9) -#define STM32_SPI_CR1_SSI (1 << 12) +#define STM32_SPI_CR1_SPE BIT(0) +#define STM32_SPI_CR1_CSTART BIT(9) +#define STM32_SPI_CR1_SSI BIT(12) #define STM32_SPI_CR1_DIV(div) ((div) << 28) #define STM32_SPI_CFG1_DATASIZE(n) (((n) - 1) << 0) #define STM32_SPI_CFG1_FTHLV(n) (((n) - 1) << 5) @@ -1783,43 +1784,43 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) #define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) #define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) -#define STM32_SPI_CFG1_RXDMAEN (1 << 14) -#define STM32_SPI_CFG1_TXDMAEN (1 << 15) +#define STM32_SPI_CFG1_RXDMAEN BIT(14) +#define STM32_SPI_CFG1_TXDMAEN BIT(15) #define STM32_SPI_CFG1_CRCSIZE(n) (((n) - 1) << 16) -#define STM32_SPI_CFG2_MSTR (1 << 22) -#define STM32_SPI_CFG2_SSM (1 << 26) -#define STM32_SPI_CFG2_AFCNTR (1 << 31) +#define STM32_SPI_CFG2_MSTR BIT(22) +#define STM32_SPI_CFG2_SSM BIT(26) +#define STM32_SPI_CFG2_AFCNTR BIT(31) -#define STM32_SPI_SR_RXNE (1 << 0) -#define STM32_SPI_SR_UDR (1 << 5) +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_UDR BIT(5) #define STM32_SPI_SR_FRLVL (3 << 13) -#define STM32_SPI_SR_TXC (1 << 12) +#define STM32_SPI_SR_TXC BIT(12) #else /* !CHIP_FAMILY_STM32H7 */ -#define STM32_SPI_CR1_BIDIMODE (1 << 15) -#define STM32_SPI_CR1_BIDIOE (1 << 14) -#define STM32_SPI_CR1_CRCEN (1 << 13) -#define STM32_SPI_CR1_SSM (1 << 9) -#define STM32_SPI_CR1_SSI (1 << 8) -#define STM32_SPI_CR1_LSBFIRST (1 << 7) -#define STM32_SPI_CR1_SPE (1 << 6) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) #define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R (1 << 3) -#define STM32_SPI_CR1_MSTR (1 << 2) -#define STM32_SPI_CR1_CPOL (1 << 1) -#define STM32_SPI_CR1_CPHA (1 << 0) -#define STM32_SPI_CR2_FRXTH (1 << 12) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) #define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE (1 << 7) -#define STM32_SPI_CR2_RXNEIE (1 << 6) -#define STM32_SPI_CR2_NSSP (1 << 3) -#define STM32_SPI_CR2_SSOE (1 << 2) -#define STM32_SPI_CR2_TXDMAEN (1 << 1) -#define STM32_SPI_CR2_RXDMAEN (1 << 0) - -#define STM32_SPI_SR_RXNE (1 << 0) -#define STM32_SPI_SR_TXE (1 << 1) -#define STM32_SPI_SR_CRCERR (1 << 4) -#define STM32_SPI_SR_BSY (1 << 7) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) #define STM32_SPI_SR_FRLVL (3 << 9) #define STM32_SPI_SR_FTLVL (3 << 11) #endif /* !CHIP_FAMILY_STM32H7 */ @@ -1845,17 +1846,17 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #if defined(CHIP_FAMILY_STM32L) #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY (1 << 0) -#define STM32_FLASH_ACR_PRFTEN (1 << 1) -#define STM32_FLASH_ACR_ACC64 (1 << 2) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(1) +#define STM32_FLASH_ACR_ACC64 BIT(2) #define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_PECR_PE_LOCK (1 << 0) -#define STM32_FLASH_PECR_PRG_LOCK (1 << 1) -#define STM32_FLASH_PECR_OPT_LOCK (1 << 2) -#define STM32_FLASH_PECR_PROG (1 << 3) -#define STM32_FLASH_PECR_ERASE (1 << 9) -#define STM32_FLASH_PECR_FPRG (1 << 10) -#define STM32_FLASH_PECR_OBL_LAUNCH (1 << 18) +#define STM32_FLASH_PECR_PE_LOCK BIT(0) +#define STM32_FLASH_PECR_PRG_LOCK BIT(1) +#define STM32_FLASH_PECR_OPT_LOCK BIT(2) +#define STM32_FLASH_PECR_PROG BIT(3) +#define STM32_FLASH_PECR_ERASE BIT(9) +#define STM32_FLASH_PECR_FPRG BIT(10) +#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) #define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF @@ -1883,8 +1884,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) #define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY (1 << 0) -#define STM32_FLASH_ACR_PRFTEN (1 << 4) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(4) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define FLASH_KEYR_KEY1 0x45670123 #define FLASH_KEYR_KEY2 0xCDEF89AB @@ -1893,21 +1894,21 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 #define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY (1 << 0) -#define FLASH_SR_PGERR (1 << 2) -#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_PGERR BIT(2) +#define FLASH_SR_WRPRTERR BIT(4) #define FLASH_SR_ALL_ERR \ (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_EOP BIT(5) #define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG (1 << 0) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_OPTPG (1 << 4) -#define FLASH_CR_OPTER (1 << 5) -#define FLASH_CR_STRT (1 << 6) -#define FLASH_CR_LOCK (1 << 7) -#define FLASH_CR_OPTWRE (1 << 9) -#define FLASH_CR_OBL_LAUNCH (1 << 13) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_OPTPG BIT(4) +#define FLASH_CR_OPTER BIT(5) +#define FLASH_CR_STRT BIT(6) +#define FLASH_CR_LOCK BIT(7) +#define FLASH_CR_OPTWRE BIT(9) +#define FLASH_CR_OBL_LAUNCH BIT(13) #define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) #define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) #define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) @@ -1926,11 +1927,11 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) #define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN (1 << 8) -#define STM32_FLASH_ACR_ICEN (1 << 9) -#define STM32_FLASH_ACR_DCEN (1 << 10) -#define STM32_FLASH_ACR_ICRST (1 << 11) -#define STM32_FLASH_ACR_DCRST (1 << 12) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define FLASH_KEYR_KEY1 0x45670123 @@ -1939,16 +1940,16 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define FLASH_OPTKEYR_KEY1 0x08192A3B #define FLASH_OPTKEYR_KEY2 0x4C5D6E7F #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_SR_BUSY (1 << 16) +#define FLASH_SR_BUSY BIT(16) #define FLASH_SR_ERR_MASK (0xc3fa) #define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_CR_PG (1 << 0) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_STRT (1 << 16) -#define FLASH_CR_OPTSTRT (1 << 17) -#define FLASH_CR_OBL_LAUNCH (1 << 27) -#define FLASH_CR_OPTLOCK (1 << 30) -#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) #define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) #define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) #define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) @@ -1971,11 +1972,11 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_SHIFT 0 #define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN (1 << 8) -#define STM32_FLASH_ACR_ICEN (1 << 9) -#define STM32_FLASH_ACR_DCEN (1 << 10) -#define STM32_FLASH_ACR_ICRST (1 << 11) -#define STM32_FLASH_ACR_DCRST (1 << 12) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define FLASH_KEYR_KEY1 0x45670123 #define FLASH_KEYR_KEY2 0xCDEF89AB @@ -1983,21 +1984,21 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define FLASH_OPTKEYR_KEY1 0x08192A3B #define FLASH_OPTKEYR_KEY2 0x4C5D6E7F #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP (1 << 0) -#define FLASH_SR_OPERR (1 << 1) -#define FLASH_SR_WRPERR (1 << 4) -#define FLASH_SR_PGAERR (1 << 5) -#define FLASH_SR_PGPERR (1 << 6) -#define FLASH_SR_PGSERR (1 << 7) -#define FLASH_SR_RDERR (1 << 8) +#define FLASH_SR_EOP BIT(0) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_PGPERR BIT(6) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_RDERR BIT(8) #define FLASH_SR_ALL_ERR \ (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY (1 << 16) +#define FLASH_SR_BUSY BIT(16) #define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG (1 << 0) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_MER BIT(2) #define STM32_FLASH_CR_SNB_OFFSET (3) #define STM32_FLASH_CR_SNB(sec) \ (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) @@ -2006,15 +2007,15 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_CR_PSIZE(size) \ (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) #define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT (1 << 16) -#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_LOCK BIT(31) #define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK (1 << 0) -#define FLASH_OPTSTRT (1 << 1) +#define FLASH_OPTLOCK BIT(0) +#define FLASH_OPTSTRT BIT(1) #define STM32_FLASH_BOR_LEV_OFFSET (2) #define STM32_FLASH_RDP_MASK (0xFF << 8) #define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) (1 << (_bank + STM32_FLASH_nWRP_OFFSET)) +#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) #define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) #define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) @@ -2023,7 +2024,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_OPTB_USER_OFF 0x02 #define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) #define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) (1 << (_bank)) +#define STM32_OPTB_nWRP(_bank) BIT(_bank) #define STM32_OPTB_nWRP_ALL (0xFF) #define STM32_OPTB_COMPL_SHIFT 8 @@ -2059,35 +2060,35 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define FLASH_OPTKEYR_KEY1 0x08192A3B #define FLASH_OPTKEYR_KEY2 0x4C5D6E7F #define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) -#define FLASH_CR_LOCK (1 << 0) -#define FLASH_CR_PG (1 << 1) -#define FLASH_CR_SER (1 << 2) -#define FLASH_CR_BER (1 << 3) +#define FLASH_CR_LOCK BIT(0) +#define FLASH_CR_PG BIT(1) +#define FLASH_CR_SER BIT(2) +#define FLASH_CR_BER BIT(3) #define FLASH_CR_PSIZE_BYTE (0 << 4) #define FLASH_CR_PSIZE_HWORD (1 << 4) #define FLASH_CR_PSIZE_WORD (2 << 4) #define FLASH_CR_PSIZE_DWORD (3 << 4) #define FLASH_CR_PSIZE_MASK (3 << 4) -#define FLASH_CR_FW (1 << 6) -#define FLASH_CR_STRT (1 << 7) +#define FLASH_CR_FW BIT(6) +#define FLASH_CR_STRT BIT(7) #define FLASH_CR_SNB(sec) (((sec) & 0x7) << 8) #define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) #define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) -#define FLASH_SR_BUSY (1 << 0) -#define FLASH_SR_WBNE (1 << 1) -#define FLASH_SR_QW (1 << 2) -#define FLASH_SR_CRC_BUSY (1 << 3) -#define FLASH_SR_EOP (1 << 16) -#define FLASH_SR_WRPERR (1 << 17) -#define FLASH_SR_PGSERR (1 << 18) -#define FLASH_SR_STRBERR (1 << 19) -#define FLASH_SR_INCERR (1 << 21) -#define FLASH_SR_OPERR (1 << 22) -#define FLASH_SR_RDPERR (1 << 23) -#define FLASH_SR_RDSERR (1 << 24) -#define FLASH_SR_SNECCERR (1 << 25) -#define FLASH_SR_DBECCERR (1 << 26) -#define FLASH_SR_CRCEND (1 << 27) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_WBNE BIT(1) +#define FLASH_SR_QW BIT(2) +#define FLASH_SR_CRC_BUSY BIT(3) +#define FLASH_SR_EOP BIT(16) +#define FLASH_SR_WRPERR BIT(17) +#define FLASH_SR_PGSERR BIT(18) +#define FLASH_SR_STRBERR BIT(19) +#define FLASH_SR_INCERR BIT(21) +#define FLASH_SR_OPERR BIT(22) +#define FLASH_SR_RDPERR BIT(23) +#define FLASH_SR_RDSERR BIT(24) +#define FLASH_SR_SNECCERR BIT(25) +#define FLASH_SR_DBECCERR BIT(26) +#define FLASH_SR_CRCEND BIT(27) #define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) #define FLASH_CCR_ERR_MASK (FLASH_SR_WRPERR | FLASH_SR_PGSERR \ | FLASH_SR_STRBERR | FLASH_SR_INCERR \ @@ -2095,18 +2096,18 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; | FLASH_SR_RDSERR | FLASH_SR_SNECCERR \ | FLASH_SR_DBECCERR) #define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) -#define FLASH_OPTCR_OPTLOCK (1 << 0) -#define FLASH_OPTCR_OPTSTART (1 << 1) +#define FLASH_OPTCR_OPTLOCK BIT(0) +#define FLASH_OPTCR_OPTSTART BIT(1) #define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) #define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) -#define FLASH_OPTSR_BUSY (1 << 0) /* only in OPTSR_CUR */ +#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ #define FLASH_OPTSR_RDP_MASK (0xFF << 8) #define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) /* RDP Level 1: Anything but 0xAA/0xCC */ #define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) #define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) -#define FLASH_OPTSR_RSS1 (1 << 26) -#define FLASH_OPTSR_RSS2 (1 << 27) +#define FLASH_OPTSR_RSS1 BIT(26) +#define FLASH_OPTSR_RSS2 BIT(27) #define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) #define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) #define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) @@ -2173,7 +2174,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ defined(CHIP_FAMILY_STM32F4) -#define EXTI_RTC_ALR_EVENT (1 << 17) +#define EXTI_RTC_ALR_EVENT BIT(17) #endif /* --- ADC --- */ @@ -2181,12 +2182,12 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) #define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) #define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON (1 << 0) -#define STM32_ADC_CR2_CONT (1 << 1) -#define STM32_ADC_CR2_CAL (1 << 2) -#define STM32_ADC_CR2_RSTCAL (1 << 3) -#define STM32_ADC_CR2_ALIGN (1 << 11) -#define STM32_ADC_CR2_SWSTART (1 << 30) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) #define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) #define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) #define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) @@ -2201,28 +2202,28 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) #elif defined(CHIP_FAMILY_STM32F0) #define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_ISR_ADRDY (1 << 0) +#define STM32_ADC_ISR_ADRDY BIT(0) #define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_IER_AWDIE (1 << 7) -#define STM32_ADC_IER_OVRIE (1 << 4) -#define STM32_ADC_IER_EOSEQIE (1 << 3) -#define STM32_ADC_IER_EOCIE (1 << 2) -#define STM32_ADC_IER_EOSMPIE (1 << 1) -#define STM32_ADC_IER_ADRDYIE (1 << 0) +#define STM32_ADC_IER_AWDIE BIT(7) +#define STM32_ADC_IER_OVRIE BIT(4) +#define STM32_ADC_IER_EOSEQIE BIT(3) +#define STM32_ADC_IER_EOCIE BIT(2) +#define STM32_ADC_IER_EOSMPIE BIT(1) +#define STM32_ADC_IER_ADRDYIE BIT(0) #define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR_ADEN (1 << 0) -#define STM32_ADC_CR_ADDIS (1 << 1) -#define STM32_ADC_CR_ADCAL (1 << 31) +#define STM32_ADC_CR_ADEN BIT(0) +#define STM32_ADC_CR_ADDIS BIT(1) +#define STM32_ADC_CR_ADCAL BIT(31) #define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ #define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26) -#define STM32_ADC_CFGR1_AWDEN (1 << 23) -#define STM32_ADC_CFGR1_AWDSGL (1 << 22) +#define STM32_ADC_CFGR1_AWDEN BIT(23) +#define STM32_ADC_CFGR1_AWDSGL BIT(22) /* Selects single vs continuous */ -#define STM32_ADC_CFGR1_CONT (1 << 13) +#define STM32_ADC_CFGR1_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC_CFGR1_OVRMOD (1 << 12) +#define STM32_ADC_CFGR1_OVRMOD BIT(12) /* External trigger polarity selection */ #define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) #define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10) @@ -2240,8 +2241,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_CFGR1_TRG7 (7 << 6) #define STM32_ADC_CFGR1_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC_CFGR1_DMACFG (1 << 1) -#define STM32_ADC_CFGR1_DMAEN (1 << 0) +#define STM32_ADC_CFGR1_DMACFG BIT(1) +#define STM32_ADC_CFGR1_DMAEN BIT(0) #define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ #define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) @@ -2310,29 +2311,29 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) #define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) -#define STM32_COMP_WNDWE (1 << 17) -#define STM32_COMP_VREFOUTEN (1 << 16) -#define STM32_COMP_CMP2OUT (1 << 13) -#define STM32_COMP_SPEED_FAST (1 << 12) +#define STM32_COMP_WNDWE BIT(17) +#define STM32_COMP_VREFOUTEN BIT(16) +#define STM32_COMP_CMP2OUT BIT(13) +#define STM32_COMP_SPEED_FAST BIT(12) -#define STM32_COMP_CMP1OUT (1 << 7) -#define STM32_COMP_CMP1EN (1 << 4) +#define STM32_COMP_CMP1OUT BIT(7) +#define STM32_COMP_CMP1EN BIT(4) -#define STM32_COMP_400KPD (1 << 3) -#define STM32_COMP_10KPD (1 << 2) -#define STM32_COMP_400KPU (1 << 1) -#define STM32_COMP_10KPU (1 << 0) +#define STM32_COMP_400KPD BIT(3) +#define STM32_COMP_10KPD BIT(2) +#define STM32_COMP_400KPU BIT(1) +#define STM32_COMP_10KPU BIT(0) #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) #define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) -#define STM32_COMP_CMP2LOCK (1 << 31) -#define STM32_COMP_CMP2OUT (1 << 30) +#define STM32_COMP_CMP2LOCK BIT(31) +#define STM32_COMP_CMP2OUT BIT(30) #define STM32_COMP_CMP2HYST_HI (3 << 28) #define STM32_COMP_CMP2HYST_MED (2 << 28) #define STM32_COMP_CMP2HYST_LOW (1 << 28) #define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL (1 << 27) +#define STM32_COMP_CMP2POL BIT(27) #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) @@ -2348,7 +2349,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) #endif #define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN (1 << 23) +#define STM32_COMP_WNDWEN BIT(23) #define STM32_COMP_CMP2INSEL_MASK (7 << 20) #define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ @@ -2364,15 +2365,15 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2MODE_LSPEED (2 << 18) #define STM32_COMP_CMP2MODE_MSPEED (1 << 18) #define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN (1 << 16) +#define STM32_COMP_CMP2EN BIT(16) -#define STM32_COMP_CMP1LOCK (1 << 15) -#define STM32_COMP_CMP1OUT (1 << 14) +#define STM32_COMP_CMP1LOCK BIT(15) +#define STM32_COMP_CMP1OUT BIT(14) #define STM32_COMP_CMP1HYST_HI (3 << 12) #define STM32_COMP_CMP1HYST_MED (2 << 12) #define STM32_COMP_CMP1HYST_LOW (1 << 12) #define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL (1 << 11) +#define STM32_COMP_CMP1POL BIT(11) #ifdef CHIP_VARIANT_STM32F373 #define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8) @@ -2407,8 +2408,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP1MODE_LSPEED (2 << 2) #define STM32_COMP_CMP1MODE_MSPEED (1 << 2) #define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 (1 << 1) -#define STM32_COMP_CMP1EN (1 << 0) +#define STM32_COMP_CMP1SW1 BIT(1) +#define STM32_COMP_CMP1EN BIT(0) #endif /* --- Routing interface --- */ /* STM32L1xx only */ @@ -2450,7 +2451,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) #define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) -#define STM32_DAC_CR_DMAEN2 (1 << 28) +#define STM32_DAC_CR_DMAEN2 BIT(28) #define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) #define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) #define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) @@ -2458,10 +2459,10 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) #define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) #define STM32_DAC_CR_TSEL2_MASK (7 << 19) -#define STM32_DAC_CR_TEN2 (1 << 18) -#define STM32_DAC_CR_BOFF2 (1 << 17) -#define STM32_DAC_CR_EN2 (1 << 16) -#define STM32_DAC_CR_DMAEN1 (1 << 12) +#define STM32_DAC_CR_TEN2 BIT(18) +#define STM32_DAC_CR_BOFF2 BIT(17) +#define STM32_DAC_CR_EN2 BIT(16) +#define STM32_DAC_CR_DMAEN1 BIT(12) #define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) #define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) #define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) @@ -2469,9 +2470,9 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) #define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) #define STM32_DAC_CR_TSEL1_MASK (7 << 3) -#define STM32_DAC_CR_TEN1 (1 << 2) -#define STM32_DAC_CR_BOFF1 (1 << 1) -#define STM32_DAC_CR_EN1 (1 << 0) +#define STM32_DAC_CR_TEN1 BIT(2) +#define STM32_DAC_CR_BOFF1 BIT(1) +#define STM32_DAC_CR_EN1 BIT(0) /* --- DMA --- */ @@ -2716,31 +2717,31 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN (1 << 0) -#define STM32_DMA_CCR_DMEIE (1 << 1) -#define STM32_DMA_CCR_TEIE (1 << 2) -#define STM32_DMA_CCR_HTIE (1 << 3) -#define STM32_DMA_CCR_TCIE (1 << 4) -#define STM32_DMA_CCR_PFCTRL (1 << 5) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) #define STM32_DMA_CCR_DIR_P2M (0 << 6) #define STM32_DMA_CCR_DIR_M2P (1 << 6) #define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC (1 << 8) -#define STM32_DMA_CCR_PINC (1 << 9) -#define STM32_DMA_CCR_MINC (1 << 10) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) #define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) #define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) #define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) #define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) #define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) #define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS (1 << 15) +#define STM32_DMA_CCR_PINCOS BIT(15) #define STM32_DMA_CCR_PL_LOW (0 << 16) #define STM32_DMA_CCR_PL_MEDIUM (1 << 16) #define STM32_DMA_CCR_PL_HIGH (2 << 16) #define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM (1 << 18) -#define STM32_DMA_CCR_CT (1 << 19) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) #define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) #define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) #ifdef CHIP_FAMILY_STM32H7 @@ -2753,7 +2754,7 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_CCR_RSVD_MASK (0xF0100000) -#define STM32_DMA_SFCR_DMDIS (1 << 2) +#define STM32_DMA_SFCR_DMDIS BIT(2) #define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) @@ -2783,11 +2784,11 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_FEIF (1 << 0) -#define STM32_DMA_DMEIF (1 << 2) -#define STM32_DMA_TEIF (1 << 3) -#define STM32_DMA_HTIF (1 << 4) -#define STM32_DMA_TCIF (1 << 5) +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) #define STM32_DMA_ALL 0x3d #else /* !CHIP_FAMILY_STM32F4 */ @@ -2809,16 +2810,16 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, 1 << 0) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, 1 << 1) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, 1 << 2) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, 1 << 3) +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) #define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) -#define STM32_DMA_GIF (1 << 0) -#define STM32_DMA_TCIF (1 << 1) -#define STM32_DMA_HTIF (1 << 2) -#define STM32_DMA_TEIF (1 << 3) +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) #define STM32_DMA_ALL 0xf #define STM32_DMA_GET_ISR(channel) \ @@ -2840,14 +2841,14 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN (1 << 0) -#define STM32_DMA_CCR_TCIE (1 << 1) -#define STM32_DMA_CCR_HTIE (1 << 2) -#define STM32_DMA_CCR_TEIE (1 << 3) -#define STM32_DMA_CCR_DIR (1 << 4) -#define STM32_DMA_CCR_CIRC (1 << 5) -#define STM32_DMA_CCR_PINC (1 << 6) -#define STM32_DMA_CCR_MINC (1 << 7) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) #define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) #define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) #define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) @@ -2858,7 +2859,7 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_CCR_PL_MEDIUM (1 << 12) #define STM32_DMA_CCR_PL_HIGH (2 << 12) #define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM (1 << 14) +#define STM32_DMA_CCR_MEM2MEM BIT(14) #endif /* !CHIP_FAMILY_STM32F4 */ #ifdef CHIP_FAMILY_STM32H7 @@ -2987,7 +2988,7 @@ enum dmamux1_request { #define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) #define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) -#define STM32_CRC_CR_RESET (1 << 0) +#define STM32_CRC_CR_RESET BIT(0) #define STM32_CRC_CR_POLYSIZE_32 (0 << 3) #define STM32_CRC_CR_POLYSIZE_16 (1 << 3) #define STM32_CRC_CR_POLYSIZE_8 (2 << 3) @@ -2995,7 +2996,7 @@ enum dmamux1_request { #define STM32_CRC_CR_REV_IN_BYTE (1 << 5) #define STM32_CRC_CR_REV_IN_HWORD (2 << 5) #define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT (1 << 7) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ #define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) @@ -3023,35 +3024,35 @@ enum dmamux1_request { #define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) -#define STM32_USB_CNTR_FRES (1 << 0) -#define STM32_USB_CNTR_PDWN (1 << 1) -#define STM32_USB_CNTR_LP_MODE (1 << 2) -#define STM32_USB_CNTR_FSUSP (1 << 3) -#define STM32_USB_CNTR_RESUME (1 << 4) -#define STM32_USB_CNTR_L1RESUME (1 << 5) -#define STM32_USB_CNTR_L1REQM (1 << 7) -#define STM32_USB_CNTR_ESOFM (1 << 8) -#define STM32_USB_CNTR_SOFM (1 << 9) -#define STM32_USB_CNTR_RESETM (1 << 10) -#define STM32_USB_CNTR_SUSPM (1 << 11) -#define STM32_USB_CNTR_WKUPM (1 << 12) -#define STM32_USB_CNTR_ERRM (1 << 13) -#define STM32_USB_CNTR_PMAOVRM (1 << 14) -#define STM32_USB_CNTR_CTRM (1 << 15) +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) #define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) #define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR (1 << 4) -#define STM32_USB_ISTR_L1REQ (1 << 7) -#define STM32_USB_ISTR_ESOF (1 << 8) -#define STM32_USB_ISTR_SOF (1 << 9) -#define STM32_USB_ISTR_RESET (1 << 10) -#define STM32_USB_ISTR_SUSP (1 << 11) -#define STM32_USB_ISTR_WKUP (1 << 12) -#define STM32_USB_ISTR_ERR (1 << 13) -#define STM32_USB_ISTR_PMAOVR (1 << 14) -#define STM32_USB_ISTR_CTR (1 << 15) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) #define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) @@ -3063,14 +3064,14 @@ enum dmamux1_request { #define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) #define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) -#define STM32_USB_BCDR_BCDEN (1 << 0) -#define STM32_USB_BCDR_DCDEN (1 << 1) -#define STM32_USB_BCDR_PDEN (1 << 2) -#define STM32_USB_BCDR_SDEN (1 << 3) -#define STM32_USB_BCDR_DCDET (1 << 4) -#define STM32_USB_BCDR_PDET (1 << 5) -#define STM32_USB_BCDR_SDET (1 << 6) -#define STM32_USB_BCDR_PS2DET (1 << 7) +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) #define EP_MASK 0x0F0F #define EP_TX_DTOG 0x0040 @@ -3097,11 +3098,11 @@ enum dmamux1_request { /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN (1<<2) -#define STM32_RNG_CR_IE (1<<3) -#define STM32_RNG_CR_CED (1<<5) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) #define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY (1<<0) +#define STM32_RNG_SR_DRDY BIT(0) #define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ @@ -3109,8 +3110,8 @@ enum dmamux1_request { /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ #define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE (1 << 1) -#define READ_ISS_OVERRIDE (1 << 0) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ #define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) diff --git a/include/battery_smart.h b/include/battery_smart.h index e4931dad71..2a36c45d7f 100644 --- a/include/battery_smart.h +++ b/include/battery_smart.h @@ -61,14 +61,14 @@ #define SB_ALT_MANUFACTURER_ACCESS 0x44 /* Battery mode */ -#define MODE_INTERNAL_CHARGE_CONTROLLER (1 << 0) -#define MODE_PRIMARY_BATTERY_SUPPORT (1 << 1) -#define MODE_CONDITION_CYCLE (1 << 7) -#define MODE_CHARGE_CONTROLLER_ENABLED (1 << 8) -#define MODE_PRIMARY_BATTERY (1 << 9) -#define MODE_ALARM (1 << 13) -#define MODE_CHARGER (1 << 14) -#define MODE_CAPACITY (1 << 15) +#define MODE_INTERNAL_CHARGE_CONTROLLER BIT(0) +#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1) +#define MODE_CONDITION_CYCLE BIT(7) +#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8) +#define MODE_PRIMARY_BATTERY BIT(9) +#define MODE_ALARM BIT(13) +#define MODE_CHARGER BIT(14) +#define MODE_CAPACITY BIT(15) /* Battery status */ #define STATUS_ERR_CODE_MASK 0xf @@ -80,16 +80,16 @@ #define STATUS_CODE_OVERUNDERFLOW 5 #define STATUS_CODE_BADSIZE 6 #define STATUS_CODE_UNKNOWN_ERROR 7 -#define STATUS_FULLY_DISCHARGED (1 << 4) -#define STATUS_FULLY_CHARGED (1 << 5) -#define STATUS_DISCHARGING (1 << 6) -#define STATUS_INITIALIZED (1 << 7) -#define STATUS_REMAINING_TIME_ALARM (1 << 8) -#define STATUS_REMAINING_CAPACITY_ALARM (1 << 9) -#define STATUS_TERMINATE_DISCHARGE_ALARM (1 << 11) -#define STATUS_OVERTEMP_ALARM (1 << 12) -#define STATUS_TERMINATE_CHARGE_ALARM (1 << 14) -#define STATUS_OVERCHARGED_ALARM (1 << 15) +#define STATUS_FULLY_DISCHARGED BIT(4) +#define STATUS_FULLY_CHARGED BIT(5) +#define STATUS_DISCHARGING BIT(6) +#define STATUS_INITIALIZED BIT(7) +#define STATUS_REMAINING_TIME_ALARM BIT(8) +#define STATUS_REMAINING_CAPACITY_ALARM BIT(9) +#define STATUS_TERMINATE_DISCHARGE_ALARM BIT(11) +#define STATUS_OVERTEMP_ALARM BIT(12) +#define STATUS_TERMINATE_CHARGE_ALARM BIT(14) +#define STATUS_OVERCHARGED_ALARM BIT(15) /* Charger alarm warning */ #define ALARM_OVER_CHARGED 0x8000 @@ -105,27 +105,27 @@ #define ALARM_STATUS_FULLY_CHARGED 0x0020 #define ALARM_STATUS_FULLY_DISCHARGED 0x0010 /* Charge mode */ -#define CHARGE_FLAG_INHIBIT_CHARGE (1 << 0) -#define CHARGE_FLAG_ENABLE_POLLING (1 << 1) -#define CHARGE_FLAG_POR_RESET (1 << 2) -#define CHARGE_FLAG_RESET_TO_ZERO (1 << 3) +#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0) +#define CHARGE_FLAG_ENABLE_POLLING BIT(1) +#define CHARGE_FLAG_POR_RESET BIT(2) +#define CHARGE_FLAG_RESET_TO_ZERO BIT(3) /* Charger status */ -#define CHARGER_CHARGE_INHIBITED (1 << 0) -#define CHARGER_POLLING_ENABLED (1 << 1) -#define CHARGER_VOLTAGE_NOTREG (1 << 2) -#define CHARGER_CURRENT_NOTREG (1 << 3) -#define CHARGER_LEVEL_2 (1 << 4) -#define CHARGER_LEVEL_3 (1 << 5) -#define CHARGER_CURRENT_OR (1 << 6) -#define CHARGER_VOLTAGE_OR (1 << 7) -#define CHARGER_RES_OR (1 << 8) -#define CHARGER_RES_COLD (1 << 9) -#define CHARGER_RES_HOT (1 << 10) -#define CHARGER_RES_UR (1 << 11) -#define CHARGER_ALARM_INHIBITED (1 << 12) -#define CHARGER_POWER_FAIL (1 << 13) -#define CHARGER_BATTERY_PRESENT (1 << 14) -#define CHARGER_AC_PRESENT (1 << 15) +#define CHARGER_CHARGE_INHIBITED BIT(0) +#define CHARGER_POLLING_ENABLED BIT(1) +#define CHARGER_VOLTAGE_NOTREG BIT(2) +#define CHARGER_CURRENT_NOTREG BIT(3) +#define CHARGER_LEVEL_2 BIT(4) +#define CHARGER_LEVEL_3 BIT(5) +#define CHARGER_CURRENT_OR BIT(6) +#define CHARGER_VOLTAGE_OR BIT(7) +#define CHARGER_RES_OR BIT(8) +#define CHARGER_RES_COLD BIT(9) +#define CHARGER_RES_HOT BIT(10) +#define CHARGER_RES_UR BIT(11) +#define CHARGER_ALARM_INHIBITED BIT(12) +#define CHARGER_POWER_FAIL BIT(13) +#define CHARGER_BATTERY_PRESENT BIT(14) +#define CHARGER_AC_PRESENT BIT(15) /* Charger specification info */ #define INFO_CHARGER_SPEC(INFO) ((INFO) & 0xf) #define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) diff --git a/include/compile_time_macros.h b/include/compile_time_macros.h index bf133d60f4..30a3e901b3 100644 --- a/include/compile_time_macros.h +++ b/include/compile_time_macros.h @@ -35,4 +35,10 @@ #define member_size(type, member) sizeof(((type *)0)->member) +/* + * Bit operation macros. + */ +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) + #endif /* __CROS_EC_COMPILE_TIME_MACROS_H */ diff --git a/include/ec_commands.h b/include/ec_commands.h index a68b0b574e..c485c49ddd 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -39,7 +39,7 @@ extern "C"{ #define EC_PROTO_VERSION 0x00000002 /* Command version mask */ -#define EC_VER_MASK(version) (1UL << (version)) +#define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ #define EC_LPC_ADDR_ACPI_DATA 0x62 @@ -65,13 +65,13 @@ extern "C"{ #define EC_HOST_CMD_REGION_SIZE 0x80 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ #define EC_LPC_ADDR_MEMMAP 0x900 #define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ @@ -129,8 +129,8 @@ extern "C"{ /* Define the format of the accelerometer mapped memory status byte. */ #define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT (1 << 4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT (1 << 7) +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ #define EC_TEMP_SENSOR_ENTRIES 16 @@ -305,8 +305,8 @@ extern "C"{ * bit 1 enables/disables the selected threshold (0 = off, 1 = on) * Each write to the commit register affects one threshold. */ -#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0) -#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1) +#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0) +#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1) /* * Example: * @@ -625,7 +625,7 @@ enum host_event_code { EC_HOST_EVENT_INVALID = 32 }; /* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1)) +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) /** * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS @@ -1153,7 +1153,7 @@ struct ec_response_get_cmd_versions { /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; /** @@ -1185,7 +1185,7 @@ struct ec_response_test_protocol { /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ -#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0) +#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0) /** * struct ec_response_get_protocol_info - Response to the get protocol info. @@ -1338,8 +1338,8 @@ enum ec_feature_code { EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, }; -#define EC_FEATURE_MASK_0(event_code) (1UL << (event_code % 32)) -#define EC_FEATURE_MASK_1(event_code) (1UL << (event_code - 32)) +#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) +#define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32) struct ec_response_get_features { uint32_t flags[2]; @@ -1382,16 +1382,19 @@ struct ec_response_flash_info { uint32_t protect_block_size; } __ec_align4; -/* Flags for version 1+ flash info command */ -/* EC flash erases bits to 0 instead of 1 */ -#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) +/* + * Flags for version 1+ flash info command + * EC flash erases bits to 0 instead of 1. + */ +#define EC_FLASH_INFO_ERASE_TO_0 BIT(0) /* Flash must be selected for read/write/erase operations to succeed. This may * be necessary on a chip where write/erase can be corrupted by other board * activity, or where the chip needs to enable some sort of programming voltage, * or where the read/write/erase operations require cleanly suspending other - * chip functionality. */ -#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) + * chip functionality. + */ +#define EC_FLASH_INFO_SELECT_REQUIRED BIT(1) /** * struct ec_response_flash_info_1 - Response to the flash info v1 command. @@ -1572,34 +1575,34 @@ struct ec_params_flash_erase_v1 { /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by * re-requesting the desired flags, or by a hard reset if that fails. */ -#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) +#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW (1 << 8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT (1 << 9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW (1 << 10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) /** @@ -2152,8 +2155,8 @@ enum ec_led_id { }; /* LED control flags */ -#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { EC_LED_COLOR_RED = 0, @@ -2488,19 +2491,19 @@ struct ec_motion_sense_activity { } __ec_todo_unpacked; /* Module flag masks used for the dump sub-command. */ -#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0) +#define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0) /* Sensor flag masks used for the dump sub-command. */ -#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0) +#define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0) /* * Flush entry for synchronization. * data contains time stamp */ -#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0) -#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1) -#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2) -#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3) +#define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0) +#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1) +#define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2) +#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3) /* * Send this value for the data element to only perform a read. If you @@ -2513,10 +2516,10 @@ struct ec_motion_sense_activity { /* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */ /* Set Calibration information */ -#define MOTION_SENSE_SET_OFFSET (1 << 0) +#define MOTION_SENSE_SET_OFFSET BIT(0) /* Default Scale value, factor 1. */ -#define MOTION_SENSE_DEFAULT_SCALE (1 << 15) +#define MOTION_SENSE_DEFAULT_SCALE BIT(15) #define LID_ANGLE_UNRELIABLE 500 @@ -2631,7 +2634,7 @@ struct ec_params_motion_sense { /* * Scale for calibration: * By default scale is 1, it is encoded on 16bits: - * 1 = 1 << 15 + * 1 = BIT(1)5 * ~2 = 0xFFFF * ~0 = 0. */ @@ -2832,7 +2835,7 @@ struct ec_params_force_lid_open { enum ec_config_power_button_flags { /* Enable/Disable power button pulses for x86 devices */ - EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0), + EC_POWER_BUTTON_ENABLE_PULSE = BIT(0), }; struct ec_params_config_power_button { @@ -3280,13 +3283,13 @@ enum mkbp_config_flags { }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = 1 << 0, - EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1, - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3, - EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4, - EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5, - EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6, - EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7, + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -3340,7 +3343,7 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0, + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; struct ec_collect_item { @@ -3394,10 +3397,10 @@ struct ec_result_keyscan_seq_ctrl { * We use the most significant bit of the event type to indicate to the host * that the EC has more MKBP events available to provide. */ -#define EC_MKBP_HAS_MORE_EVENTS (1 << EC_MKBP_HAS_MORE_EVENTS_SHIFT) +#define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) /* The mask to apply to get the raw event type */ -#define EC_MKBP_EVENT_TYPE_MASK ((1 << EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) +#define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1) enum ec_mkbp_event { /* Keyboard matrix changed. The event data is the new matrix state. */ @@ -3535,11 +3538,11 @@ struct ec_response_keyboard_factory_test { #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 #define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ >> EC_MKBP_FP_MATCH_IDX_OFFSET) -#define EC_MKBP_FP_ENROLL (1 << 27) -#define EC_MKBP_FP_MATCH (1 << 28) -#define EC_MKBP_FP_FINGER_DOWN (1 << 29) -#define EC_MKBP_FP_FINGER_UP (1 << 30) -#define EC_MKBP_FP_IMAGE_READY (1 << 31) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ #define EC_MKBP_FP_ERR_ENROLL_OK 0 #define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 @@ -3888,7 +3891,7 @@ struct ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN (1 << 0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) struct ec_params_battery_cutoff { uint8_t flags; @@ -3959,13 +3962,13 @@ struct ec_response_power_info { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ (1 << 15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ #define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK (1 << 0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT (1 << 1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) @@ -3995,27 +3998,27 @@ struct ec_response_i2c_passthru { /* Reasons to start hang detection timer */ /* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS (1 << 0) +#define EC_HANG_START_ON_POWER_PRESS BIT(0) /* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE (1 << 1) +#define EC_HANG_START_ON_LID_CLOSE BIT(1) /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN (1 << 2) +#define EC_HANG_START_ON_LID_OPEN BIT(2) /* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME (1 << 3) +#define EC_HANG_START_ON_RESUME BIT(3) /* Reasons to cancel hang detection */ /* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8) +#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) /* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND (1 << 9) +#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) /* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND (1 << 10) +#define EC_HANG_STOP_ON_SUSPEND BIT(10) /* * If this flag is set, all the other fields are ignored, and the hang detect @@ -4023,14 +4026,14 @@ struct ec_response_i2c_passthru { * without reconfiguring any of the other hang detect settings. Note that * you must previously have configured the timeouts. */ -#define EC_HANG_START_NOW (1 << 30) +#define EC_HANG_START_NOW BIT(30) /* * If this flag is set, all the other fields are ignored (including * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer * without reconfiguring any of the other hang detect settings. */ -#define EC_HANG_STOP_NOW (1 << 31) +#define EC_HANG_STOP_NOW BIT(31) struct ec_params_hang_detect { /* Flags; see EC_HANG_* */ @@ -4232,7 +4235,7 @@ enum ec_device_event_param { EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS, }; -#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32)) +#define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32) struct ec_params_device_event { uint32_t event_mask; @@ -4468,9 +4471,9 @@ enum cec_command { /* Events from CEC to AP */ enum mkbp_cec_event { /* Outgoing message was acknowledged by a follower */ - EC_MKBP_CEC_SEND_OK = 1 << 0, + EC_MKBP_CEC_SEND_OK = BIT(0), /* Outgoing message was not acknowledged */ - EC_MKBP_CEC_SEND_FAILED = 1 << 1, + EC_MKBP_CEC_SEND_FAILED = BIT(1), }; /*****************************************************************************/ @@ -4495,9 +4498,9 @@ enum ec_reboot_cmd { }; /* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ struct ec_params_reboot_ec { uint8_t cmd; /* enum ec_reboot_cmd */ @@ -4571,7 +4574,7 @@ enum pd_charge_state { }; /* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING (1 << 0) +#define EC_STATUS_HIBERNATING BIT(0) struct ec_params_pd_status { uint8_t status; /* EC status */ @@ -4580,13 +4583,13 @@ struct ec_params_pd_status { } __ec_align1; /* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT (1 << 0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW (1 << 1) /* Running RW image */ -#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 (1 << 3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 (1 << 4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 (1 << 5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 (1 << 6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ #define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ PD_STATUS_TCPC_ALERT_1 | \ PD_STATUS_HOST_EVENT) @@ -4600,10 +4603,10 @@ struct ec_response_pd_status { #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE (1 << 0) -#define PD_EVENT_POWER_CHANGE (1 << 1) -#define PD_EVENT_IDENTITY_RECEIVED (1 << 2) -#define PD_EVENT_DATA_SWAP (1 << 3) +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) struct ec_response_host_event_status { uint32_t status; /* PD MCU host event status */ } __ec_align4; @@ -4646,17 +4649,17 @@ struct ec_params_usb_pd_control { uint8_t swap; } __ec_align1; -#define PD_CTRL_RESP_ENABLED_COMMS (1 << 0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED (1 << 1) /* Device connected */ -#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */ +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ -#define PD_CTRL_RESP_ROLE_POWER (1 << 0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA (1 << 1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN (1 << 2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER (1 << 3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA (1 << 4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM (1 << 5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_EXT_POWERED (1 << 6) /* Partner externally powerd */ +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +#define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6) /* Partner externally powerd */ struct ec_response_usb_pd_control { uint8_t enabled; @@ -4848,11 +4851,11 @@ struct ec_response_pd_log { * the data field contains the port state flags as defined below : */ /* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE (1 << 15) +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) /* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE (1 << 14) +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) /* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE (1 << 13) +#define CHARGE_FLAGS_OVERRIDE BIT(13) /* Charger type */ #define CHARGE_FLAGS_TYPE_SHIFT 3 #define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) @@ -4949,10 +4952,10 @@ struct ec_params_usb_pd_mux_info { } __ec_align1; /* Flags representing mux state */ -#define USB_PD_MUX_USB_ENABLED (1 << 0) -#define USB_PD_MUX_DP_ENABLED (1 << 1) -#define USB_PD_MUX_POLARITY_INVERTED (1 << 2) -#define USB_PD_MUX_HPD_IRQ (1 << 3) +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ @@ -5043,7 +5046,7 @@ enum cbi_data_tag { * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify * write was successful without reboot. */ -#define CBI_GET_RELOAD (1 << 0) +#define CBI_GET_RELOAD BIT(0) struct ec_params_get_cbi { uint32_t tag; /* enum cbi_data_tag */ @@ -5058,8 +5061,8 @@ struct ec_params_get_cbi { * INIT: Need to be set when creating a new CBI from scratch. All fields * will be initialized to zero first. */ -#define CBI_SET_NO_SYNC (1 << 0) -#define CBI_SET_INIT (1 << 1) +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) struct ec_params_set_cbi { uint32_t tag; /* enum cbi_data_tag */ @@ -5228,23 +5231,23 @@ struct ec_params_fp_passthru { #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP (1<<0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN (1<<1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP (1<<2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE (1<<3) +#define FP_MODE_CAPTURE BIT(3) /* Finger enrollment session on-going */ -#define FP_MODE_ENROLL_SESSION (1<<4) +#define FP_MODE_ENROLL_SESSION BIT(4) /* Enroll the current finger image */ -#define FP_MODE_ENROLL_IMAGE (1<<5) +#define FP_MODE_ENROLL_IMAGE BIT(5) /* Try to match the current finger image */ -#define FP_MODE_MATCH (1<<6) +#define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ -#define FP_MODE_RESET_SENSOR (1<<7) +#define FP_MODE_RESET_SENSOR BIT(7) /* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE (1<<31) +#define FP_MODE_DONT_CHANGE BIT(31) #define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ FP_MODE_FINGER_DOWN | \ @@ -5298,13 +5301,13 @@ struct ec_response_fp_mode { /* Unknown number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ -#define FP_ERROR_NO_IRQ (1 << 12) +#define FP_ERROR_NO_IRQ BIT(12) /* SPI communication error */ -#define FP_ERROR_SPI_COMM (1 << 13) +#define FP_ERROR_SPI_COMM BIT(13) /* Invalid sensor Hardware ID */ -#define FP_ERROR_BAD_HWID (1 << 14) +#define FP_ERROR_BAD_HWID BIT(14) /* Sensor initialization failed */ -#define FP_ERROR_INIT_FAIL (1 << 15) +#define FP_ERROR_INIT_FAIL BIT(15) struct ec_response_fp_info_v0 { /* Sensor identification */ @@ -5411,8 +5414,8 @@ struct ec_params_fp_context { #define EC_CMD_FP_STATS 0x0407 -#define FPSTATS_CAPTURE_INV (1 << 0) -#define FPSTATS_MATCHING_INV (1 << 1) +#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_MATCHING_INV BIT(1) struct ec_response_fp_stats { uint32_t capture_time_us; |