config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI

Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the
host interface selection configs distinct from configs used to
enable/disable specific host commands.

BUG=b:195416058
BRANCH=main
TEST=compare_build.sh

Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842
Tested-by: Michał Barnaś <mb@semihalf.com>

79 files changed, 128 insertions, 127 deletions

diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h
index 19f8aef126..e402ba7516 100644
--- a/baseboard/brask/baseboard.h
+++ b/baseboard/brask/baseboard.h
@@ -41,7 +41,7 @@
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
 /* Host communication */
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h
index 9d12792dbe..129fb5836e 100644
--- a/baseboard/brya/baseboard.h
+++ b/baseboard/brya/baseboard.h
@@ -45,7 +45,7 @@
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
 /* Host communication */
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
 /*
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 5bd80ca53b..54c7a6a24a 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -185,7 +185,7 @@ __override int power_signal_get_level(enum gpio_signal signal)
 	if (signal == GPIO_PG_EC_ALL_SYS_PWRGD)
 		return intel_x86_get_pg_ec_all_sys_pwrgd();
 
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
 			return espi_vw_get_wire((enum espi_vw_signal)signal);
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index 7357b1a5ce..529e011f32 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -121,7 +121,7 @@
 /* EC Modules */
 #define CONFIG_ADC
 #define CONFIG_CRC8
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_EVENTS
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
index 6960524822..d9aa034392 100644
--- a/baseboard/guybrush/baseboard.h
+++ b/baseboard/guybrush/baseboard.h
@@ -92,7 +92,7 @@
 
 /* Host communication */
 #define CONFIG_CMD_CHARGEN
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
 #define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index 853c1e30ff..6c9cef25fb 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -122,7 +122,7 @@
 
 /* SoC / PCH */
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define CONFIG_MKBP_EVENT
diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h
index 94ced2f989..717d26b313 100644
--- a/baseboard/kalista/baseboard.h
+++ b/baseboard/kalista/baseboard.h
@@ -63,7 +63,7 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h
index f0ecab4d87..cb75bd0c1e 100644
--- a/baseboard/octopus/baseboard.h
+++ b/baseboard/octopus/baseboard.h
@@ -249,7 +249,7 @@
  /* Common SoC / PCH defines */
 #define CONFIG_CHIPSET_GEMINILAKE
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 /* TODO(b/74123961): Enable Virtual Wires after bringup */
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_S0IX
diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h
index 31764d9c12..fd90b20b9e 100644
--- a/baseboard/volteer/baseboard.h
+++ b/baseboard/volteer/baseboard.h
@@ -43,7 +43,7 @@
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
 /* Host communication */
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
 /* Chipset config */
diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h
index d84ebbcef8..e97bcb4e45 100644
--- a/baseboard/zork/baseboard.h
+++ b/baseboard/zork/baseboard.h
@@ -38,7 +38,7 @@
 #define CONFIG_CMD_AP_RESET_LOG
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 #define CONFIG_HIBERNATE_PSL
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_UPDATE_IF_CHANGED
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
index 59af6cf877..00b4aefa3e 100644
--- a/board/adlrvpp_ite/gpio.inc
+++ b/board/adlrvpp_ite/gpio.inc
@@ -77,11 +77,11 @@ GPIO(USBC_TCPC_ALRT_P3,		PIN(J, 3), GPIO_INPUT)
 GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(E, 6), GPIO_INPUT)
 #endif
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INPUT)
 #endif
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 /* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
 GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
 #endif
@@ -112,7 +112,7 @@ GPIO(SYS_PWROK_EC,	PIN(D, 1), GPIO_OUT_LOW)
 GPIO(DSW_PWROK_EC,	PIN(L, 6), GPIO_OUT_LOW)
 
 /* Host communication GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(PLT_RST_L, 	PIN(H, 6), GPIO_INPUT | GPIO_PULL_UP) /* PCH_PLTRST_L */
 #endif
 GPIO(PCH_WAKE_N,	PIN(J, 0), GPIO_ODR_HIGH)
diff --git a/board/adlrvpp_mchp1521/gpio.inc b/board/adlrvpp_mchp1521/gpio.inc
index fd20e16568..5ec398903e 100644
--- a/board/adlrvpp_mchp1521/gpio.inc
+++ b/board/adlrvpp_mchp1521/gpio.inc
@@ -105,7 +105,7 @@ UNIMPLEMENTED(EN_PP5000)
 GPIO(SMC_WAKE_SCI_N,	PIN(0114),	GPIO_ODR_HIGH)
 /* EC_INT_L pin */
 GPIO(EC_TRACE_DATA_0,	PIN(0200),	GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(ESPI_RST_EC_R_N,	PIN(061),	GPIO_INPUT)
 #endif
 
diff --git a/board/adlrvpp_mchp1727/gpio.inc b/board/adlrvpp_mchp1727/gpio.inc
index 1eea86462c..42973648b4 100644
--- a/board/adlrvpp_mchp1727/gpio.inc
+++ b/board/adlrvpp_mchp1727/gpio.inc
@@ -83,7 +83,7 @@ GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(0142), GPIO_INPUT)
 /* Host communication GPIOs */
 GPIO(SMC_WAKE_SCI_N_MECC,	PIN(051), GPIO_ODR_HIGH)
 GPIO(EC_PCH_MKBP_INT_ODL,	PIN(0127), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(LPC_ESPI_RST_N,		PIN(061), GPIO_INPUT)
 GPIO(PLT_RST_L, 		PIN(052), GPIO_INPUT) /* PCH_PLTRST_L */
 #endif
diff --git a/board/adlrvpp_npcx/gpio.inc b/board/adlrvpp_npcx/gpio.inc
index a059b1c6b6..4a696e4c09 100644
--- a/board/adlrvpp_npcx/gpio.inc
+++ b/board/adlrvpp_npcx/gpio.inc
@@ -62,7 +62,7 @@ GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(F, 3), GPIO_INPUT)
 /* Host communication GPIOs */
 GPIO(SMC_WAKE_SCI_N_MECC,	PIN(A, 4), GPIO_ODR_HIGH)
 GPIO(EC_PCH_MKBP_INT_ODL,	PIN(F, 5), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(LPC_ESPI_RST_N,		PIN(5, 4), GPIO_INPUT | GPIO_SEL_1P8V)
 GPIO(PLT_RST_L, 		PIN(A, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PLTRST_L */
 #endif
diff --git a/board/akemi/board.h b/board/akemi/board.h
index 524607d8bb..af580a02b0 100644
--- a/board/akemi/board.h
+++ b/board/akemi/board.h
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/ambassador/board.h b/board/ambassador/board.h
index 4ca9966873..14b9260509 100644
--- a/board/ambassador/board.h
+++ b/board/ambassador/board.h
@@ -38,7 +38,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc
index 724d9a98d9..8b0a433842 100644
--- a/board/ampton/gpio.inc
+++ b/board/ampton/gpio.inc
@@ -32,7 +32,7 @@ GPIO_INT(RSMRST_L_PGOOD, PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* PM
 GPIO_INT(ALL_SYS_PGOOD,	 PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)	/* PMIC_EC_PWROK_OD */
 GPIO_INT(AC_PRESENT, 	 PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)		/* ACOK_OD */
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 /* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
 GPIO_INT(ESPI_RESET_L, 	 PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
 #endif
diff --git a/board/atlas/board.h b/board/atlas/board.h
index df2a2ee2c2..6fdf77b0f0 100644
--- a/board/atlas/board.h
+++ b/board/atlas/board.h
@@ -54,7 +54,7 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
diff --git a/board/dooly/board.h b/board/dooly/board.h
index 4e0f4a5481..d5baf98410 100644
--- a/board/dooly/board.h
+++ b/board/dooly/board.h
@@ -73,7 +73,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/dratini/board.h b/board/dratini/board.h
index 12074e3447..dfa234cb86 100644
--- a/board/dratini/board.h
+++ b/board/dratini/board.h
@@ -17,7 +17,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
diff --git a/board/endeavour/board.h b/board/endeavour/board.h
index fd1b3e5b9c..9b0107b2c4 100644
--- a/board/endeavour/board.h
+++ b/board/endeavour/board.h
@@ -58,7 +58,7 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/eve/board.h b/board/eve/board.h
index 64e299bc54..5dcb9fc32f 100644
--- a/board/eve/board.h
+++ b/board/eve/board.h
@@ -72,7 +72,7 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/fizz/board.h b/board/fizz/board.h
index 8e8cbcd823..ad1ca85cac 100644
--- a/board/fizz/board.h
+++ b/board/fizz/board.h
@@ -70,7 +70,7 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/genesis/board.h b/board/genesis/board.h
index 7c32579440..8a31b9500b 100644
--- a/board/genesis/board.h
+++ b/board/genesis/board.h
@@ -38,7 +38,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/hatch/board.h b/board/hatch/board.h
index 487c8c25eb..3867ffd819 100644
--- a/board/hatch/board.h
+++ b/board/hatch/board.h
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/helios/board.h b/board/helios/board.h
index dcda6e01fe..a29dda1adf 100644
--- a/board/helios/board.h
+++ b/board/helios/board.h
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc
index 52df89e5cb..505f91ad64 100644
--- a/board/it83xx_evb/gpio.inc
+++ b/board/it83xx_evb/gpio.inc
@@ -9,7 +9,7 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
 #endif
 GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_DOWN, lid_interrupt)
diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc
index 8a7f593ab6..e5e7d5e942 100644
--- a/board/it8xxx2_evb/gpio.inc
+++ b/board/it8xxx2_evb/gpio.inc
@@ -9,7 +9,7 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH | GPIO_PULL_UP,   power_button_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,   lpcrst_interrupt)
 #endif
 GPIO_INT(LID_OPEN,       PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP,   lid_interrupt)
diff --git a/board/jinlon/board.h b/board/jinlon/board.h
index 944413591b..1e3d287009 100644
--- a/board/jinlon/board.h
+++ b/board/jinlon/board.h
@@ -19,7 +19,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc
index 5c0219263e..387020100e 100644
--- a/board/jslrvp_ite/gpio.inc
+++ b/board/jslrvp_ite/gpio.inc
@@ -37,7 +37,7 @@ GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UAR
 
 GPIO_INT(WP_L,      PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)     /* EC_WP_ODL */
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 /* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
 GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
 #endif
@@ -72,7 +72,7 @@ UNIMPLEMENTED(EN_VCCIO_EXT)
 
 /* Host communication GPIOs */
 GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
 #endif
 
@@ -139,7 +139,7 @@ GPIO(NC_PMIC_EN,		PIN(H, 3), GPIO_INPUT)
 /* Used if Base EC is present */
 GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
 #endif
 
diff --git a/board/kindred/board.h b/board/kindred/board.h
index dd63efb390..89cd18bcc0 100644
--- a/board/kindred/board.h
+++ b/board/kindred/board.h
@@ -18,7 +18,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/kohaku/board.h b/board/kohaku/board.h
index b8470d9ba7..5217cd6b3b 100644
--- a/board/kohaku/board.h
+++ b/board/kohaku/board.h
@@ -19,7 +19,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h
index de1e7a75e9..e16d0bb10f 100644
--- a/board/mchpevb1/board.h
+++ b/board/mchpevb1/board.h
@@ -163,7 +163,7 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
index 8be1099fbd..3949e31843 100644
--- a/board/mchpevb1/gpio.inc
+++ b/board/mchpevb1/gpio.inc
@@ -27,8 +27,8 @@
 
 #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
 
-/* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */
-#ifndef CONFIG_HOSTCMD_ESPI
+/* Only needed if CONFIG_HOST_INTERFACE_ESPI is not set, using LPC interface to PCH */
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_BOTH_EDGES_PU, lpcrst_interrupt)
 #endif
 
diff --git a/board/moonbuggy/board.h b/board/moonbuggy/board.h
index 4ec5233f6f..6dfaa73d53 100644
--- a/board/moonbuggy/board.h
+++ b/board/moonbuggy/board.h
@@ -38,7 +38,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/mushu/board.h b/board/mushu/board.h
index 493ef442df..aadd49a1bd 100644
--- a/board/mushu/board.h
+++ b/board/mushu/board.h
@@ -23,7 +23,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #undef CONFIG_CMD_MFALLOW
 
 
diff --git a/board/nami/board.h b/board/nami/board.h
index 1753ec538f..5952b1a754 100644
--- a/board/nami/board.h
+++ b/board/nami/board.h
@@ -73,7 +73,7 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
diff --git a/board/nautilus/board.h b/board/nautilus/board.h
index 6be7167538..b4a05e46d1 100644
--- a/board/nautilus/board.h
+++ b/board/nautilus/board.h
@@ -62,7 +62,7 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/nightfury/board.h b/board/nightfury/board.h
index 86191e104d..9c4ac02934 100644
--- a/board/nightfury/board.h
+++ b/board/nightfury/board.h
@@ -20,7 +20,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
index 70da6ac3ae..7f44e0d48e 100644
--- a/board/nocturne/board.h
+++ b/board/nocturne/board.h
@@ -30,7 +30,7 @@
 /* EC modules */
 #define CONFIG_ADC
 #define CONFIG_BACKLIGHT_LID
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_I2C
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 #define CONFIG_I2C_CONTROLLER
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
index 4bad61b152..ab8b850d94 100644
--- a/board/npcx7_evb/board.h
+++ b/board/npcx7_evb/board.h
@@ -28,7 +28,7 @@
 #define CONFIG_SPI
 #define CONFIG_I2C
 /* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h
index e7e1190480..a0d209c938 100644
--- a/board/npcx9_evb/board.h
+++ b/board/npcx9_evb/board.h
@@ -13,7 +13,7 @@
 #define CONFIG_PWM
 #define CONFIG_I2C
 /* Features of eSPI */
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 
diff --git a/board/palkia/board.h b/board/palkia/board.h
index 010bfb908b..510c5aa6da 100644
--- a/board/palkia/board.h
+++ b/board/palkia/board.h
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/poppy/board.h b/board/poppy/board.h
index 98fcfdbfa9..ca287c7c6e 100644
--- a/board/poppy/board.h
+++ b/board/poppy/board.h
@@ -63,7 +63,7 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
diff --git a/board/puff/board.h b/board/puff/board.h
index 9330d128ef..2fcbea6d61 100644
--- a/board/puff/board.h
+++ b/board/puff/board.h
@@ -38,7 +38,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/rammus/board.h b/board/rammus/board.h
index c084d98fb0..24df8218ca 100644
--- a/board/rammus/board.h
+++ b/board/rammus/board.h
@@ -58,7 +58,7 @@
 #define CONFIG_CHIPSET_SKYLAKE
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
 #define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc
index 9882065d50..ac2fbf486e 100644
--- a/board/reef_it8320/gpio.inc
+++ b/board/reef_it8320/gpio.inc
@@ -20,7 +20,7 @@ GPIO_INT(PCH_SLP_S0_L,		PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt)				/*
 #endif
 GPIO_INT(SUSPWRDNACK,		PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt)	/* SUSPWRNACK */
 GPIO_INT(LID_OPEN,		PIN(E, 2), GPIO_INT_BOTH, lid_interrupt)		/* LID_OPEN */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(PCH_PLTRST_L,   	PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP,  lpcrst_interrupt)	/* PLT_RST_L */
 #endif
 GPIO_INT(POWER_BUTTON_L,	PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
diff --git a/board/scout/board.h b/board/scout/board.h
index 5a09624b15..c90e1acda9 100644
--- a/board/scout/board.h
+++ b/board/scout/board.h
@@ -38,7 +38,7 @@
 #define CONFIG_MKBP_USE_HOST_EVENT
 #undef CONFIG_KEYBOARD_RUNTIME_KEYS
 #undef CONFIG_HIBERNATE
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
 #undef  CONFIG_LID_SWITCH
 #define CONFIG_LTO
diff --git a/board/stryke/board.h b/board/stryke/board.h
index d84a09fe36..9708f70518 100644
--- a/board/stryke/board.h
+++ b/board/stryke/board.h
@@ -16,7 +16,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc
index e0bce1ddd8..b84c92aac6 100644
--- a/board/tglrvpu_ite/gpio.inc
+++ b/board/tglrvpu_ite/gpio.inc
@@ -37,7 +37,7 @@ GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UAR
 
 GPIO_INT(WP_L,		PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 /* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
 GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
 #endif
@@ -75,7 +75,7 @@ GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
 
 /* Host communication GPIOs */
 GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
 #endif
 
@@ -165,7 +165,7 @@ GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
 /* Used if Base EC is present */
 GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
 #endif
 
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index bbff9f009b..cffd7c68f8 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -29,7 +29,7 @@ chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DAC)+=dac.o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
 chip-$(CONFIG_SPI)+=spi.o
 chip-$(CONFIG_PECI)+=peci.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 41f800721a..72cfa3e2b4 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -232,7 +232,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
 				1, 1, 5, 1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 		/*
 		 * Workaround for (b:70537592):
 		 * We have to set chip select pin as input mode in order to
@@ -249,7 +249,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 #endif
 		/* Update PLL settings. */
 		clock_pll_changed();
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
 		/* Enable eSPI pad after changing PLL sequence. */
 		espi_enable_pad(1);
@@ -301,7 +301,8 @@ void clock_init(void)
 	 */
 	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40;
 
-#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(IT83XX_ESPI_RESET_MODULE_BY_FW) && \
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Because we don't support eSPI HW reset function (b/111480168) on DX
 	 * version, so we have to reset eSPI configurations during init to
@@ -539,7 +540,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	/* EC sleep */
 	ec_sleep = 1;
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
 	/* Disable eSPI pad. */
 	espi_enable_pad(0);
 #endif
@@ -565,7 +566,7 @@ void clock_sleep_mode_wakeup_isr(void)
 	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
 	if (clock_ec_wake_from_sleep()) {
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOSTCMD_ESPI)
+defined(CONFIG_HOST_INTERFACE_ESPI)
 		/*
 		 * Enable eSPI pad.
 		 * We will not need to enable eSPI pad here if Dx is able to
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index be02a8f813..5542d455a9 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -20,7 +20,7 @@ static const struct ec2i_t keyboard_settings[] = {
 	/* Set IRQ=01h for logical device */
 	{HOST_INDEX_IRQNUMX, 0x01},
 	/* Configure IRQTP for KBC. */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Interrupt request type select (IRQTP) for KBC.
 	 * bit 1, 0: IRQ request is buffered and applied to SERIRQ
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 5e6fd734c4..45fff30c1e 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -84,7 +84,7 @@ static void intc_cpu_int_group_12(void)
 		peci_interrupt();
 		break;
 #endif
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	case IT83XX_IRQ_ESPI:
 		espi_interrupt();
 		break;
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 867d9e024f..8a90bd426d 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -136,7 +136,7 @@ static void keyboard_irq_assert(void)
  */
 static void lpc_generate_smi(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SMI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SMI_L, 1);
@@ -149,7 +149,7 @@ static void lpc_generate_smi(void)
 
 static void lpc_generate_sci(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SCI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SCI_L, 1);
@@ -377,7 +377,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
 	pm_set_status(LPC_ACPI_CMD, mask, 0);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 int lpc_get_pltrst_asserted(void)
 {
 	return !gpio_get_level(GPIO_PCH_PLTRST_L);
@@ -688,7 +688,7 @@ static void lpc_init(void)
 	 */
 	IT83XX_GCTRL_SPCTRL1 |= 0xC2;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	gpio_enable_interrupt(GPIO_PCH_PLTRST_L);
 #endif
 
@@ -711,7 +711,7 @@ static void lpc_init(void)
 	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
 	task_enable_irq(IT83XX_IRQ_PMC3_IN);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_init();
 #endif
 	/* Sufficiently initialized */
@@ -726,7 +726,7 @@ static void lpc_init(void)
  */
 DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal)
 {
 	if (lpc_get_pltrst_asserted())
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 2fde34f8f0..39aba42315 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1456,7 +1456,7 @@ enum bram_indices {
 	BRAM_IDX_EC_LOG_STATUS = 0xc,
 
 	/* offset 0x0d ~ 0x1f are reserved for future use. */
-#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * offset 0x20 ~ 0x7b are reserved for future use.
 	 * (apply to x86 platform)
@@ -1508,7 +1508,7 @@ enum bram_ec_logs_status {
  * And they will be used to save panic data if the GPG1 reset mechanism
  * is enabled.
  */
-#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 /* offset 0x80 ~ 0xbf */
 #define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
 #else
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 9725ba4525..ae7fd627bf 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -50,7 +50,7 @@ static void clear_reset_flags(void)
 }
 DECLARE_HOOK(HOOK_INIT, clear_reset_flags, HOOK_PRIO_LAST);
 
-#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_HOST_INTERFACE_LPC) && !defined(CONFIG_HOST_INTERFACE_ESPI)
 static void system_save_panic_data_to_bram(void)
 {
 	uint8_t *ptr = (uint8_t *)PANIC_DATA_PTR;
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 155fbf385f..226fe23363 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -32,7 +32,7 @@ endif
 chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index 362025ee1c..7a3914194b 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -395,7 +395,7 @@ static void prepare_for_deep_sleep(void)
 #endif
 
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 #else
@@ -475,7 +475,7 @@ static void resume_from_deep_sleep(void)
 	 */
 	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
index a7db914f3b..778990b852 100644
--- a/chip/mchp/espi.c
+++ b/chip/mchp/espi.c
@@ -1386,7 +1386,7 @@ void espi_init(void)
 				(CONFIG_HOSTCMD_ESPI_EC_MODE
 				<< MCHP_ESPI_CAP1_IO_BITPOS);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
 #else
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 9f6a731eb5..9e64281276 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -88,7 +88,7 @@ static void keyboard_irq_assert(void)
 static void lpc_generate_smi(void)
 {
 	CPUTS("LPC Pulse SMI");
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* eSPI: pulse SMI# Virtual Wire low */
 	espi_vw_pulse_wire(VW_SMI_L, 0);
 #else
@@ -106,7 +106,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
 #else
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_pulse_wire(VW_SCI_L, 0);
 #else
 	MCHP_ACPI_PM_STS |= 1;
@@ -129,7 +129,7 @@ static void lpc_update_wake(host_event_t wake_events)
 	 */
 	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_WAKE_L, !wake_events);
 #else
 	/* Signal is asserted low when wake events is non-zero */
@@ -304,7 +304,7 @@ const int acpi_ec_nvic_ibf[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 const int acpi_ec_espi_bar_id[] = {
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
@@ -326,7 +326,7 @@ void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
 
 	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
 			mask;
 	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
@@ -350,7 +350,7 @@ void chip_8042_config(uint32_t io_base)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
 			(io_base << 16) + 0x01ul;
@@ -372,7 +372,7 @@ void chip_8042_config(uint32_t io_base)
 #ifndef CONFIG_KEYBOARD_IRQ_GPIO
 	/* Set up SERIRQ for keyboard */
 	MCHP_8042_KB_CTRL |= BIT(5);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
 	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
 #else
@@ -392,7 +392,7 @@ void chip_8042_config(uint32_t io_base)
  */
 void chip_emi0_config(uint32_t io_base)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
 			(io_base << 16) + 0x01ul;
@@ -442,7 +442,7 @@ void chip_port80_config(uint32_t io_base)
 	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
 			MCHP_P80_RESET_TIMESTAMP_WO;
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
 	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
 			(io_base << 16) + 0x01ul;
@@ -484,7 +484,7 @@ static void chip_lpc_iobar_debug(void)
  * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
  *
  */
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 static void setup_lpc(void)
 {
 	MCHP_LPC_CFG_BAR |= (1ul << 15);
@@ -545,7 +545,7 @@ static void lpc_init(void)
 		MCHP_PCR_SLP_EN2_ACPI_EC0 +
 		MCHP_PCR_SLP_EN2_MIF8042);
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 	espi_init();
 
@@ -621,7 +621,7 @@ void lpc_set_init_done(int val)
  */
 void lpcrst_interrupt(enum gpio_signal signal)
 {
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/* Initialize LPC module when LRESET# is de-asserted */
 	if (!lpc_get_pltrst_asserted()) {
 		setup_lpc();
@@ -941,10 +941,10 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
  */
 int lpc_get_pltrst_asserted(void)
 {
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * eSPI PLTRST# a VWire or side-band signal
-	 * Controlled by CONFIG_HOSTCMD_ESPI
+	 * Controlled by CONFIG_HOST_INTERFACE_ESPI
 	 */
 	return !espi_vw_get_wire(VW_PLTRST_L);
 #else
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
index dcb5577fc1..434b307968 100644
--- a/chip/mchp/lpc_chip.h
+++ b/chip/mchp/lpc_chip.h
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_LPC_CHIP_H
 #define __CROS_EC_LPC_CHIP_H
 
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 
 #include "espi.h"
 
@@ -37,7 +37,7 @@ void lpc_set_init_done(int val);
 
 void lpc_mem_mapped_init(void);
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 void lpcrst_interrupt(enum gpio_signal signal);
 #endif
 
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
index 5591c818c4..72c96bef8f 100644
--- a/chip/mchp/system.c
+++ b/chip/mchp/system.c
@@ -178,7 +178,7 @@ void system_pre_init(void)
 	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
 
 	/* Manual voltage selection only required for MEC170x and MEC152x */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
 		vtr3_voltage_select(1);
 	else
 		vtr3_voltage_select(0);
@@ -427,7 +427,7 @@ int system_get_scratchpad(uint32_t *value)
  * defined for MEC170x and the IS_ENABLED() macro causes the
  * compiler to evaluate both true and false code paths.
  */
-#if defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_ESPI)
 static void disable_host_ifc_clocks(void)
 {
 	MCHP_ESPI_ACTIVATE &= ~0x01;
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 3a41cfbd53..f872b2d051 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -33,7 +33,7 @@ chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
 chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
-chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 chip-$(CONFIG_PECI)+=peci.o
 chip-$(CONFIG_HOSTCMD_SHI)+=shi.o
 chip-$(CONFIG_CEC)+=cec.o
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index ad611973be..ab3bd7f119 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -422,7 +422,7 @@ void __idle(void)
 			 * CSAE bit is set. Please notice this symptom only
 			 * occurs at npcx5.
 			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI)
 			/* Enable Host access wakeup */
 			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
index c6fcf7351b..8e7c76abf1 100644
--- a/chip/npcx/gpio-npcx5.c
+++ b/chip/npcx/gpio-npcx5.c
@@ -67,7 +67,7 @@ static void __gpio_wk0efgh_interrupt(void)
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
 				&&
 			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
index e9e8ad2ad9..c5b7e900f7 100644
--- a/chip/npcx/gpio-npcx9.c
+++ b/chip/npcx/gpio-npcx9.c
@@ -70,7 +70,7 @@ static void __gpio_host_interrupt(void)
 			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
 					&&
 			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 9bb2de8936..c80bf2960b 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -86,7 +86,7 @@ static void lpc_task_enable_irq(void)
 #endif
 	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_enable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_enable_irq(NPCX_IRQ_WKINTA_2);
@@ -105,7 +105,7 @@ static void lpc_task_disable_irq(void)
 #endif
 	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	task_disable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_disable_irq(NPCX_IRQ_WKINTA_2);
@@ -137,7 +137,7 @@ static void lpc_generate_smi(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -183,7 +183,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_HOSTCMD_ESPI)
+#elif defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -698,7 +698,7 @@ void host_register_init(void)
 	 * EC hardware will put those 4 bytes of Port80 code to DP80BUF FIFO.
 	 * This is only supported when CHIP_FAMILY >= NPCX9.
 	 */
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI))
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI))
 		sib_write_reg(SIO_OFFSET, 0xFD, 0x0F);
 	/* enable SHM */
 	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
@@ -721,7 +721,7 @@ int lpc_get_pltrst_asserted(void)
 	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
 }
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 /* Initialize host settings by interrupt */
 void lpc_lreset_pltrst_handler(void)
 {
@@ -771,7 +771,7 @@ static void lpc_init(void)
 	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
 	 * field should be set by firmware.
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	/* Initialize eSPI module */
 	NPCX_DEVCNT |= 0x08;
 	espi_init();
@@ -787,7 +787,7 @@ static void lpc_init(void)
 	/* Clear Host Access Hold state */
 	NPCX_SMC_CTL = 0xC0;
 
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
 	 * continuous or quiet mode.
@@ -800,7 +800,7 @@ static void lpc_init(void)
 	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
 	 * automatically by toggling them, too. It's unnecessary to set pin mux.
 	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOST_INTERFACE_ESPI)
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
 #endif
@@ -876,7 +876,7 @@ static void lpc_init(void)
 	 * Init PORT80
 	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
 	 */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 	NPCX_DP80CTL = 0x2b;
 #else
 	NPCX_DP80CTL = 0x29;
@@ -926,7 +926,7 @@ static void lpc_init(void)
 	/* initial IO port address via SIB-write modules */
 	host_register_init();
 #else
-#ifndef CONFIG_HOSTCMD_ESPI
+#ifndef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
 	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
index b62946fc96..424048518e 100644
--- a/chip/npcx/sib.c
+++ b/chip/npcx/sib.c
@@ -19,7 +19,7 @@
  * For eSPI - it is 200 us.
  * For LPC - it is 5 us.
  */
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 #define HOST_TRANSACTION_TIMEOUT_US 200
 #else
 #define HOST_TRANSACTION_TIMEOUT_US 5
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index ac7056330f..97fcd01c41 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -872,7 +872,7 @@ void system_pre_init(void)
 		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
 #endif
 		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_HOSTCMD_ESPI)
+#if !defined(CONFIG_HOST_INTERFACE_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
diff --git a/common/build.mk b/common/build.mk
index 901d0d3c9d..bd0fcb164e 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -83,7 +83,7 @@ common-$(CONFIG_DEVICE_STATE)+=device_state.o
 common-$(CONFIG_DPTF)+=dptf.o
 common-$(CONFIG_EC_EC_COMM_CLIENT)+=ec_ec_comm_client.o
 common-$(CONFIG_EC_EC_COMM_SERVER)+=ec_ec_comm_server.o
-common-$(CONFIG_HOSTCMD_ESPI)+=espi.o
+common-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o
 common-$(CONFIG_EXTPOWER_GPIO)+=extpower_gpio.o
 common-$(CONFIG_EXTPOWER)+=extpower_common.o
 common-$(CONFIG_FANS)+=fan.o pwm.o
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index fa5642cca6..487387db86 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -79,7 +79,7 @@ void __idle(void)
 		 * CSAE bit is set. Please notice this symptom only
 		 * occurs at npcx5.
 		 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOST_INTERFACE_ESPI)
 		/* Enable Host access wakeup */
 		SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
diff --git a/core/nds32/init.S b/core/nds32/init.S
index b8e109c434..159f3709d3 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -87,7 +87,7 @@ vector irq_15,   15	/* HW 15 */
 .global eflash_sig
 eflash_sig:
 .byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 .byte 0xA4 /* eSPI */
 #else
 .byte 0xA5 /* LPC */
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S
index 5715478356..8ee5479e0e 100644
--- a/core/riscv-rv32i/init.S
+++ b/core/riscv-rv32i/init.S
@@ -75,7 +75,7 @@ __ec_intc:
 .global eflash_sig
 eflash_sig:
 .byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_HOSTCMD_ESPI
+#ifdef CONFIG_HOST_INTERFACE_ESPI
 .byte 0xA4 /* eSPI */
 #else
 .byte 0xA5 /* LPC */
diff --git a/docs/configuration/config_ap_to_ec_comm.md b/docs/configuration/config_ap_to_ec_comm.md
index eb8ffa47db..c19f781936 100644
--- a/docs/configuration/config_ap_to_ec_comm.md
+++ b/docs/configuration/config_ap_to_ec_comm.md
@@ -12,7 +12,7 @@ following options.
 -   `CONFIG_HOSTCMD_SHI` - [SPI Host Interface](../ec_terms.md#shi) (SHI)
 -   `CONFIG_HOST_INTERFACE_HECI` - HECI interface
 -   `CONFIG_HOST_INTERFACE_LPC` - [LPC](../ec_terms.md#lpc) bus
--   `CONFIG_HOSTCMD_ESPI` - [eSPI](../ec_terms.md#espi) bus
+-   `CONFIG_HOST_INTERFACE_ESPI` - [eSPI](../ec_terms.md#espi) bus
 
 In [config.h], search for options that start with the same name as your selected
 communication interface. Override defaults as needed.
diff --git a/include/config.h b/include/config.h
index 724b06ac5e..8ec78bf174 100644
--- a/include/config.h
+++ b/include/config.h
@@ -3146,14 +3146,14 @@
 /*
  * EC supports x86 host communication with AP. This can either be through LPC
  * or eSPI. The CONFIG_HOSTCMD_X86 will get automatically defined if either
- * CONFIG_HOST_INTERFACE_LPC or CONFIG_HOSTCMD_ESPI are defined.
+ * CONFIG_HOST_INTERFACE_LPC or CONFIG_HOST_INTERFACE_ESPI are defined.
  * LPC and eSPI are mutually exclusive.
  */
 #undef CONFIG_HOSTCMD_X86
 /* Support host command interface over LPC bus. */
 #undef CONFIG_HOST_INTERFACE_LPC
 /* Support host command interface over eSPI bus. */
-#undef CONFIG_HOSTCMD_ESPI
+#undef CONFIG_HOST_INTERFACE_ESPI
 
 /*
  * SLP signals (SLP_S3 and SLP_S4) use virtual wires intead of physical pins
@@ -5516,7 +5516,7 @@
  * without using eSPI for host commands.
  */
 #if (!defined(CONFIG_ZEPHYR) && defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && \
-     !defined(CONFIG_HOSTCMD_ESPI))
+	!defined(CONFIG_HOST_INTERFACE_ESPI))
 #error Must enable eSPI to enable virtual wires.
 #endif
 
@@ -5641,17 +5641,17 @@
  * Automatically define CONFIG_HOSTCMD_X86 if either child option is defined.
  * Ensure LPC and eSPI are mutually exclusive
  */
-#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 #define CONFIG_HOSTCMD_X86
 #endif
 
-#if defined(CONFIG_HOST_INTERFACE_LPC) && defined(CONFIG_HOSTCMD_ESPI)
+#if defined(CONFIG_HOST_INTERFACE_LPC) && defined(CONFIG_HOST_INTERFACE_ESPI)
 #error Must select only one type of host communication bus.
 #endif
 
 #if defined(CONFIG_HOSTCMD_X86) && \
 	!defined(CONFIG_HOST_INTERFACE_LPC) && \
-	!defined(CONFIG_HOSTCMD_ESPI)
+	!defined(CONFIG_HOST_INTERFACE_ESPI)
 #error Must select one type of host communication bus.
 #endif
 
diff --git a/power/common.c b/power/common.c
index f3dbdb55f1..0db4eb8f3e 100644
--- a/power/common.c
+++ b/power/common.c
@@ -151,7 +151,7 @@ int power_signal_is_asserted(const struct power_signal_info *s)
 #ifdef CONFIG_BRINGUP
 static const char *power_signal_get_name(enum gpio_signal signal)
 {
-	if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+	if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
 		/* Check signal is from GPIOs or VWs */
 		if (espi_signal_is_vw(signal))
 			return espi_vw_get_wire_name(
diff --git a/util/config_allowed.txt b/util/config_allowed.txt
index 99a442f1fa..be80cd1721 100644
--- a/util/config_allowed.txt
+++ b/util/config_allowed.txt
@@ -488,7 +488,6 @@ CONFIG_HOSTCMD_ALIGNED
 CONFIG_HOSTCMD_AP_SET_SKUID
 CONFIG_HOSTCMD_BATTERY_V2
 CONFIG_HOSTCMD_BUTTON
-CONFIG_HOSTCMD_ESPI
 CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
 CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
 CONFIG_HOSTCMD_ESPI_EC_MODE
@@ -518,6 +517,7 @@ CONFIG_HOST_ESPI_VW_POWER_SIGNAL
 CONFIG_HOST_EVENT64
 CONFIG_HOST_EVENT64_REPORT_MASK
 CONFIG_HOST_EVENT_REPORT_MASK
+CONFIG_HOST_INTERFACE_ESPI
 CONFIG_HOST_INTERFACE_HECI
 CONFIG_HOST_INTERFACE_LPC
 CONFIG_HWTIMER_64BIT
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 9598e2cf5a..3033248e1b 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -334,7 +334,7 @@
 #ifdef CONFIG_PLATFORM_EC_ESPI
 
 #ifdef CONFIG_PLATFORM_EC_HOSTCMD
-#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_HOST_INTERFACE_ESPI
 #endif
 
 /* eSPI signals */