diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-03-03 09:48:25 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-03-03 15:36:30 +0000 |
| commit | 3827e7bdc32950ce637d5f9c8cfb1817f7f2b830 (patch) | |
| tree | f675046fd04c6b26be984f1448a61434f819ba2b | |
| parent | 42b70db2224624979897b8a5a28062164bad9dd6 (diff) | |
| download | chrome-ec-3827e7bdc32950ce637d5f9c8cfb1817f7f2b830.tar.gz | |
npcx: gpio: Fixed bug GPIO's ISRs clear the other pending bits.
Since the interrupts of MIWU group E/F/G/H of table 0 are the same
(interrupt 11), we need to handle LPCs' and GPIOs' events at the
same ISR. But we also found there is a leak that ec has the chance
to skip the other events which don't belong to GPIOs unexpectedly.
(For example, LRESET and eSPI Reset) This CL fixed this issue by
only clearing pending bits belong to GPIOs in their ISRs.
BRANCH=none
BUG=b:35648154
TEST=passed warm-reset testing on pyro over 12 hours.
Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449474
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
| -rw-r--r-- | chip/npcx/gpio.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index f0beddbfc0..3ddd2ee41e 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -761,14 +761,15 @@ static void gpio_interrupt(int int_no) if (!wui_mask) continue; - /* Clear pending bits of WUI */ - NPCX_WKPCL(i, j) = wui_mask; - for (pin = 0; pin < 8; pin++, gpio++) - /* If pending bit is high, execute ISR*/ - if (wui_mask & (1 << pin)) + /* If GPIO's pending bit is set, execute ISR */ + if ((wui_mask & (1 << pin)) && gpio->valid) { + /* Clear pending bit of GPIO */ + NPCX_WKPCL(i, j) = (1 << pin); + /* Execute GPIO's ISR */ gpio_execute_isr(gpio->port, 1 << gpio->bit); + } } } } |