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authorPhilip Chen <philipchen@google.com>2018-11-15 10:59:15 -0800
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2018-11-20 22:35:11 +0000
commit5bb2905aaa1aaf78664eff507cbc25cad7a6f2ca (patch)
tree4e934e61717514c560cd8924a99828bbbf8051b7
parent80f0e301768cf7e53cc98a5fcd6dc593dfecd597 (diff)
downloadchrome-ec-5bb2905aaa1aaf78664eff507cbc25cad7a6f2ca.tar.gz
power/rk3399: Remove unused power_seq_version
The current power_seq_version 1 is only for Scarlet rev0, which is not supported anymore. BUG=b:119617491 BRANCH=scarlet TEST=manually test on dru, confirm S5->S0->S5 and S0->S3->S0 still work fine Change-Id: I0784cecddd3911f057998eb21b8edb5c577431e5 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1344797 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Trybot-Ready: Philip Chen <philipchen@chromium.org>
-rw-r--r--board/scarlet/board.h2
-rw-r--r--power/rk3399.c28
2 files changed, 12 insertions, 18 deletions
diff --git a/board/scarlet/board.h b/board/scarlet/board.h
index b3d9bd1772..08840e6c3a 100644
--- a/board/scarlet/board.h
+++ b/board/scarlet/board.h
@@ -41,7 +41,7 @@
/* Enable a different power-on sequence than the one on gru */
#undef CONFIG_CHIPSET_POWER_SEQ_VERSION
-#define CONFIG_CHIPSET_POWER_SEQ_VERSION 2
+#define CONFIG_CHIPSET_POWER_SEQ_VERSION 1
/* Optional features */
#define CONFIG_BOARD_PRE_INIT
diff --git a/power/rk3399.c b/power/rk3399.c
index 049d07a489..2ee7c729d3 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -8,10 +8,8 @@
/*
* The description of each CONFIG_CHIPSET_POWER_SEQ_VERSION:
*
- * Version 0: Initial/default revision.
- * Version 1: Control signals PP900_PLL_EN and PP900_PMU_EN
- * are merged with PP900_USB_EN.
- * Version 2: Simplified power tree, fewer control signals.
+ * Version 0: Initial/default revision for clamshell / convertible.
+ * Version 1: Simplified power tree for tablet / detachable.
*/
#include "charge_state.h"
@@ -35,7 +33,7 @@
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
/* Input state flags */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
#define IN_PGOOD_PP1250_S3 POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
#define IN_PGOOD_PP900_S0 POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
#else
@@ -47,7 +45,7 @@
#define IN_SUSPEND_DEASSERTED POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
/* Rails requires for S3 and S0 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
#define IN_PGOOD_S3 (IN_PGOOD_PP1250_S3)
#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
/* This board can optionally wake-on-USB in S3 */
@@ -92,7 +90,7 @@ BUILD_ASSERT(GPIO_COUNT < 256);
* to the bottom.
*/
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
static const struct power_seq_op s5s3_power_seq[] = {
{ GPIO_PP900_S3_EN, 1, 2 },
{ GPIO_PP3300_S3_EN, 1, 2 },
@@ -104,10 +102,8 @@ static const struct power_seq_op s5s3_power_seq[] = {
{ GPIO_PPVAR_LOGIC_EN, 1, 0 },
{ GPIO_PP900_AP_EN, 1, 0 },
{ GPIO_PP900_PCIE_EN, 1, 2 },
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 0
{ GPIO_PP900_PMU_EN, 1, 0 },
{ GPIO_PP900_PLL_EN, 1, 0 },
-#endif
{ GPIO_PP900_USB_EN, 1, 2 },
{ GPIO_SYS_RST_L, 0, 0 },
{ GPIO_PP1800_PMU_EN_L, 0, 2 },
@@ -123,7 +119,7 @@ static const struct power_seq_op s5s3_power_seq[] = {
#endif
/* The power sequence for POWER_S3S0 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
static const struct power_seq_op s3s0_power_seq[] = {
{ GPIO_AP_CORE_EN, 1, 2 },
{ GPIO_PP1800_S0_EN, 1, 0 },
@@ -149,7 +145,7 @@ static const struct power_seq_op s3s0_usb_wake_power_seq[] = {
#endif
/* The power sequence for POWER_S0S3 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
static const struct power_seq_op s0s3_power_seq[] = {
{ GPIO_AP_CORE_EN, 0, 20 },
};
@@ -175,7 +171,7 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = {
#endif
/* The power sequence for POWER_S3S5 */
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
static const struct power_seq_op s3s5_power_seq[] = {
{ GPIO_SYS_RST_L, 0, 0 },
{ GPIO_PP1250_S3_EN, 0, 2 },
@@ -194,10 +190,8 @@ static const struct power_seq_op s3s5_power_seq[] = {
{ GPIO_PP1800_USB_EN_L, 1, 10 },
{ GPIO_LPDDR_PWR_EN, 0, 20 },
{ GPIO_PP1800_PMU_EN_L, 1, 2 },
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 0
{ GPIO_PP900_PLL_EN, 0, 0 },
{ GPIO_PP900_PMU_EN, 0, 0 },
-#endif
{ GPIO_PP900_USB_EN, 0, 6 },
{ GPIO_PP900_PCIE_EN, 0, 0 },
{ GPIO_PP900_AP_EN, 0, 0 },
@@ -350,7 +344,7 @@ enum power_state power_handle_state(enum power_state state)
!(power_get_signals() & IN_SUSPEND_DEASSERTED))
return POWER_S0S3;
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 1
/*
* Wait up to PGOOD_AP_DEBOUNCE_TIMEOUT for IN_PGOOD_AP to
* come back before transitioning back to S3. PGOOD_SYS can
@@ -541,7 +535,7 @@ static void power_button_changed(void)
if (power_button_is_pressed()) {
if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION != 1
/* Power up from off */
chipset_exit_hard_off();
#else
@@ -552,7 +546,7 @@ static void power_button_changed(void)
hook_call_deferred(&force_shutdown_data,
FORCED_SHUTDOWN_DELAY);
} else {
-#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+#if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
if (tablet_boot_on_button_release) {
/* Power up from off */
chipset_exit_hard_off();