diff options
| author | Jes B. Klinke <jbk@chromium.org> | 2023-02-27 14:45:21 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-28 18:55:04 +0000 |
| commit | 956ccf53021f8896166ecb0fb912480d14109cd3 (patch) | |
| tree | 4b735bfeb735334bd4a838617560f4b79dc90b7a | |
| parent | 1f597aa3c8b4d12d7d3c1e92fda4f9925d405750 (diff) | |
| download | chrome-ec-956ccf53021f8896166ecb0fb912480d14109cd3.tar.gz | |
board/hyperdebug: Calculate SPI speed depending on clock speed
Previous SPI code computed clock divisors based on the assumption that
the "peripheral clock" was 16Mhz. I have since increased the core
clock, and peripheral clock with it, to 104Mhz, in order to improve
performance.
This CL adds code to take the higher base clock into account when
computing the divisor required to achieve a certain SPI clock speed.
Also, if the requested QSPI speed is slower than what can be achieved
with 8-bit divisor, clamp at the slowest possible speed (406 kbps).
These SPI speeds are faster than what I would have liked. The STM32L5
chip supports a clock divisor between the core CPU clock and the
peripheral clocks, which could have helped, but the EC codebase does not
support it, and gets the UART speed calculations wrong if used.
BUG=266832220
TEST=Observed opentitantool being able to flash via SPI
Change-Id: I35ba83c978d8a6ac845a8a703cab4a9de0f486aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4295368
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
| -rw-r--r-- | board/hyperdebug/spi.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/board/hyperdebug/spi.c b/board/hyperdebug/spi.c index ed63b33017..51270ca91d 100644 --- a/board/hyperdebug/spi.c +++ b/board/hyperdebug/spi.c @@ -13,19 +13,19 @@ #include "usb_spi.h" #include "util.h" -#define OCTOSPI_CLOCK (16000000UL) -#define SPI_CLOCK (16000000UL) +#define OCTOSPI_CLOCK (CPU_CLOCK) +#define SPI_CLOCK (CPU_CLOCK) -/* SPI devices, default to 250 kb/s for all. */ +/* SPI devices, default to 406 kb/s for all. */ struct spi_device_t spi_devices[] = { { .name = "SPI2", .port = 1, - .div = 5, + .div = 7, .gpio_cs = GPIO_CN9_25, .usb_flags = USB_SPI_ENABLED }, { .name = "QSPI", .port = -1 /* OCTOSPI */, - .div = 63, + .div = 255, .gpio_cs = GPIO_CN10_6, .usb_flags = USB_SPI_ENABLED | USB_SPI_CUSTOM_SPI_DEVICE }, }; @@ -121,9 +121,11 @@ static int command_spi_set_speed(int argc, const char **argv) * slightly slower speed than requested, if it cannot be matched * exactly. */ - spi_devices[index].div = + int divisor = (OCTOSPI_CLOCK + desired_speed - 1) / desired_speed - 1; - STM32_OCTOSPI_DCR2 = spi_devices[index].div; + if (divisor >= 256) + divisor = 255; + STM32_OCTOSPI_DCR2 = spi_devices[index].div = divisor; } else { int divisor = 7; /* |