zephyr/emul: Add ANX7483 emulator

Add ANX7483 emulator and associated tests.

BRANCH=none
BUG=b:247151116
TEST=Ran tests

Change-Id: Idd56a90e58c6d482556d92446aa0659a6a1b8105
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4322379
Reviewed-by: Diana Z <dzigterman@chromium.org>

12 files changed, 1789 insertions, 22 deletions

diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c
index f04a71a1a3..3cb840dfa5 100644
--- a/driver/retimer/anx7483.c
+++ b/driver/retimer/anx7483.c
@@ -181,18 +181,19 @@ static struct anx7483_tuning_set anx7483_dock_flip[] = {
 	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
 };
 
-static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val)
+test_export_static int anx7483_read(const struct usb_mux *me, uint8_t reg,
+				    int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx7483_write(const struct usb_mux *me, uint8_t reg,
-				uint8_t val)
+test_export_static int anx7483_write(const struct usb_mux *me, uint8_t reg,
+				     uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static int anx7483_init(const struct usb_mux *me)
+test_export_static int anx7483_init(const struct usb_mux *me)
 {
 	timestamp_t start;
 	int rv;
@@ -222,8 +223,8 @@ static int anx7483_init(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state,
-		       bool *ack_required)
+test_export_static int anx7483_set(const struct usb_mux *me,
+				   mux_state_t mux_state, bool *ack_required)
 {
 	int reg;
 	int val;
@@ -265,7 +266,8 @@ static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state,
 	return anx7483_write(me, ANX7483_ANALOG_STATUS_CTRL_REG, reg);
 }
 
-static int anx7483_get(const struct usb_mux *me, mux_state_t *mux_state)
+test_export_static int anx7483_get(const struct usb_mux *me,
+				   mux_state_t *mux_state)
 {
 	int reg;
 
diff --git a/zephyr/Kconfig.retimer b/zephyr/Kconfig.retimer
index 245964711d..ea16f2bd3c 100644
--- a/zephyr/Kconfig.retimer
+++ b/zephyr/Kconfig.retimer
@@ -88,15 +88,6 @@ config PLATFORM_EC_USBC_RETIMER_ANX7451
 	  ANX7451 has built-in re-timers to recover both the USB and DP signals
 	  with loss compensation of 23dB for USB and up to 27dB for DP.
 
-config PLATFORM_EC_USBC_RETIMER_ANX7483
-	bool "Support Analogix ANX7483 10G Active Retimer"
-	default y
-	depends on DT_HAS_ANALOGIX_ANX7483_ENABLED
-	help
-	  ANX7483 is a 4x4 re-driver capable of switching DisplayPort and
-	  USB3.2 Gen 2 10Gbps signals to support type-C (USB-C) ports with
-	  DisplayPort Alternate Mode.
-
 config PLATFORM_EC_USBC_RETIMER_PS8818
 	bool "Parade PS8818 USB Type-C Retimer for USB and DP Alternate Mode"
 	default y
@@ -126,6 +117,15 @@ config PLATFORM_EC_KB800X_CUSTOM_XBAR
 
 endif # PLATFORM_EC_USBC
 
+config PLATFORM_EC_USBC_RETIMER_ANX7483
+	bool "Support Analogix ANX7483 10G Active Retimer"
+	default y
+	depends on DT_HAS_ANALOGIX_ANX7483_ENABLED && (PLATFORM_EC_USBC || TEST_DISABLE_PLATFORM_EC_USBC)
+	help
+	  ANX7483 is a 4x4 re-driver capable of switching DisplayPort and
+	  USB3.2 Gen 2 10Gbps signals to support type-C (USB-C) ports with
+	  DisplayPort Alternate Mode.
+
 config PLATFORM_EC_USBC_RETIMER_PS8811
 	bool "Support Parade PS8811 Single Port USB 3.1 Gen 2 10G Retimer"
 	depends on PLATFORM_EC_USBC || TEST_DISABLE_PLATFORM_EC_USBC
diff --git a/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml b/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml
new file mode 100644
index 0000000000..2b871c62a0
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,anx7483-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr ANX7483 emulator
+
+compatible: "cros,anx7483-emul"
+
+include: base.yaml
diff --git a/zephyr/emul/retimer/CMakeLists.txt b/zephyr/emul/retimer/CMakeLists.txt
index 52c6741ac3..33af461d1d 100644
--- a/zephyr/emul/retimer/CMakeLists.txt
+++ b/zephyr/emul/retimer/CMakeLists.txt
@@ -2,4 +2,5 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-zephyr_library_sources_ifdef(CONFIG_EMUL_PS8811 emul_ps8811.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_ANX7483 emul_anx7483.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_PS8811 emul_ps8811.c)
\ No newline at end of file
diff --git a/zephyr/emul/retimer/Kconfig b/zephyr/emul/retimer/Kconfig
index 1f4c84f34e..e37470771f 100644
--- a/zephyr/emul/retimer/Kconfig
+++ b/zephyr/emul/retimer/Kconfig
@@ -2,6 +2,13 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+config EMUL_ANX7483
+	bool "ANX7483 Emulator"
+	depends on DT_HAS_CROS_ANX7483_EMUL_ENABLED
+	default y
+	help
+	  Enable emulator for ANX7483 retimer.
+
 config EMUL_PS8811
 	bool "Parade PS8811 Emulator"
 	depends on DT_HAS_CROS_PS8811_EMUL_ENABLED
diff --git a/zephyr/emul/retimer/emul_anx7483.c b/zephyr/emul/retimer/emul_anx7483.c
new file mode 100644
index 0000000000..af26b62dcc
--- /dev/null
+++ b/zephyr/emul/retimer/emul_anx7483.c
@@ -0,0 +1,333 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "driver/retimer/anx7483.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
+#include "emul/retimer/emul_anx7483.h"
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+LOG_MODULE_REGISTER(anx7483_emul, CONFIG_RETIMER_EMUL_LOG_LEVEL);
+
+#define DT_DRV_COMPAT cros_anx7483_emul
+
+struct register_config {
+	uint8_t reg;
+	uint8_t def;
+	uint8_t reserved;
+};
+
+static const struct register_config register_configs[] = {
+	{
+		.reg = ANX7483_LFPS_TIMER_REG,
+		.def = ANX7483_LFPS_TIMER_REG_DEFAULT,
+		.reserved = ANX7483_LFPS_TIMER_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_ANALOG_STATUS_CTRL_REG,
+		.def = ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT,
+		.reserved = ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+		.def = ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT,
+		.reserved = ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_AUX_SNOOPING_CTRL_REG,
+		.def = ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT,
+		.reserved = ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK,
+	},
+
+	/* CFG0 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG0_REG,
+		.def = ANX7483_UTX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG0_REG,
+		.def = ANX7483_UTX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG0_REG,
+		.def = ANX7483_URX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG0_REG,
+		.def = ANX7483_URX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG0_REG,
+		.def = ANX7483_DRX1_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG0_REG,
+		.def = ANX7483_DRX2_PORT_CFG0_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK,
+	},
+
+	/* CFG1 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG1_REG,
+		.def = ANX7483_UTX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG1_REG,
+		.def = ANX7483_UTX2_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG1_REG,
+		.def = ANX7483_URX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG1_REG,
+		.def = ANX7483_URX2_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG1_REG,
+		.def = ANX7483_DRX1_PORT_CFG1_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG1_REG,
+		.def = ANX7483_DRX2_PORT_CFG1_REG_DEFAULT,
+	},
+
+	/* CFG2 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG2_REG,
+		.def = ANX7483_UTX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG2_REG,
+		.def = ANX7483_UTX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG2_REG,
+		.def = ANX7483_URX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG2_REG,
+		.def = ANX7483_URX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG2_REG,
+		.def = ANX7483_DRX1_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG2_REG,
+		.def = ANX7483_DRX2_PORT_CFG2_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK,
+	},
+
+	/* CFG3 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG3_REG,
+		.def = ANX7483_UTX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG3_REG,
+		.def = ANX7483_UTX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG3_REG,
+		.def = ANX7483_URX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG3_REG,
+		.def = ANX7483_URX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG3_REG,
+		.def = ANX7483_DRX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG3_REG,
+		.def = ANX7483_DRX2_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DTX1_PORT_CFG3_REG,
+		.def = ANX7483_DTX1_PORT_CFG3_REG_DEFAULT,
+	},
+	{
+		.reg = ANX7483_DTX2_PORT_CFG3_REG,
+		.def = ANX7483_DTX2_PORT_CFG3_REG_DEFAULT,
+	},
+
+	/* CFG4 */
+	{
+		.reg = ANX7483_UTX1_PORT_CFG4_REG,
+		.def = ANX7483_UTX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_UTX2_PORT_CFG4_REG,
+		.def = ANX7483_UTX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX1_PORT_CFG4_REG,
+		.def = ANX7483_URX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_URX2_PORT_CFG4_REG,
+		.def = ANX7483_URX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX1_PORT_CFG4_REG,
+		.def = ANX7483_DRX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DRX2_PORT_CFG4_REG,
+		.def = ANX7483_DRX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DTX1_PORT_CFG4_REG,
+		.def = ANX7483_DTX1_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DTX1_PORT_CFG4_REG_RESERVED_MASK,
+	},
+	{
+		.reg = ANX7483_DTX2_PORT_CFG4_REG,
+		.def = ANX7483_DTX2_PORT_CFG4_REG_DEFAULT,
+		.reserved = ANX7483_DTX2_PORT_CFG4_REG_RESERVED_MASK,
+	},
+
+};
+
+static int anx7483_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int byte)
+{
+	/* Registers are only one byte. */
+	if (byte != 0)
+		return -EIO;
+
+	return (anx7483_emul_get_reg(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static int anx7483_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
+{
+	/* Registers are only one byte. */
+	if (bytes != 1)
+		return -EIO;
+	return (anx7483_emul_set_reg(emul, reg, val) == 0) ? 0 : -EIO;
+}
+
+static const struct register_config *get_reg_config(int reg)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(register_configs); i++) {
+		if (register_configs[i].reg == reg)
+			return &register_configs[i];
+	}
+
+	return NULL;
+}
+
+int anx7483_emul_get_reg(const struct emul *emulator, int reg, uint8_t *val)
+{
+	struct anx7483_emul_data *anx7483 = emulator->data;
+	const struct register_config *config = get_reg_config(reg);
+
+	if (!config) {
+		LOG_DBG("Unknown register %x", reg);
+		return -EINVAL;
+	}
+
+	*val = anx7483->regs[reg];
+	return 0;
+}
+
+int anx7483_emul_set_reg(const struct emul *emulator, int reg, uint8_t val)
+{
+	struct anx7483_emul_data *anx7483 = emulator->data;
+	const struct register_config *config = get_reg_config(reg);
+
+	if (!config) {
+		LOG_DBG("Unknown register %x", reg);
+		return -EINVAL;
+	}
+
+	if ((val & config->reserved) != (config->def & config->reserved)) {
+		LOG_DBG("Reserved bits modified for reg %02x, val: %02x, \
+			default: %02x, reserved: %02x",
+			reg, val, config->def, config->reserved);
+		return -EINVAL;
+	}
+
+	if (reg >= ARRAY_SIZE(anx7483->regs)) {
+		LOG_DBG("Register %x is out of bounds", reg);
+		return -EINVAL;
+	}
+
+	anx7483->regs[reg] = val;
+	return 0;
+}
+
+void anx7483_emul_reset(const struct emul *emul)
+{
+	/* Use the setter helps catch any default misconfigs. */
+	for (size_t i = 0; i < ARRAY_SIZE(register_configs); i++)
+		anx7483_emul_set_reg(emul, register_configs[i].reg,
+				     register_configs[i].def);
+}
+
+static int anx7483_emul_init(const struct emul *emul,
+			     const struct device *parent)
+{
+	struct anx7483_emul_data *data = emul->data;
+
+	anx7483_emul_reset(emul);
+	i2c_common_emul_init(&data->common);
+
+	return 0;
+}
+
+#define ANX7483_EMUL_RESET_RULE_AFTER(n) \
+	anx7483_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
+static void anx7483_emul_test_reset(const struct ztest_unit_test *test,
+				    void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(ANX7483_EMUL_RESET_RULE_AFTER)
+}
+
+ZTEST_RULE(emul_anx7483_reset, NULL, anx7483_emul_test_reset);
+
+#define ANX7483_EMUL(n)                                                   \
+	static struct anx7483_emul_data anx7483_emul_data_##n = { \
+		.common = { \
+			.read_byte = anx7483_emul_read_byte, \
+			.write_byte = anx7483_emul_write_byte, \
+		}, \
+	};       \
+	static const struct anx7483_emul_cfg anx7483_emul_cfg_##n = { \
+		.common = { \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
+			.data = &anx7483_emul_data_##n.common, \
+			.addr = DT_INST_REG_ADDR(n), \
+		}, \
+	};   \
+	EMUL_DT_INST_DEFINE(n, anx7483_emul_init, &anx7483_emul_data_##n, \
+			    &anx7483_emul_cfg_##n, &i2c_common_emul_api, NULL)
+
+DT_INST_FOREACH_STATUS_OKAY(ANX7483_EMUL)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE)
diff --git a/zephyr/include/emul/retimer/emul_anx7483.h b/zephyr/include/emul/retimer/emul_anx7483.h
new file mode 100644
index 0000000000..6062853bb4
--- /dev/null
+++ b/zephyr/include/emul/retimer/emul_anx7483.h
@@ -0,0 +1,108 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_ANX7483_H
+#define __EMUL_ANX7483_H
+
+#include "driver/retimer/anx7483.h"
+#include "emul/emul_common_i2c.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#define ANX7483_LFPS_TIMER_REG_RESERVED_MASK GENMASK(7, 4)
+#define ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK \
+	(GENMASK(7, 6) | GENMASK(3, 3))
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK GENMASK(7, 1)
+#define ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK GENMASK(7, 3)
+
+#define ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK GENMASK(3, 0)
+
+#define ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+#define ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK GENMASK(3, 0)
+
+#define ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DTX1_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+#define ANX7483_DTX2_PORT_CFG4_REG_RESERVED_MASK (GENMASK(7, 5) | GENMASK(3, 2))
+
+#define ANX7483_LFPS_TIMER_REG_DEFAULT 0x00
+#define ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT 0x20
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT 0x00
+#define ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT ANX7483_AUX_SNOOPING_DEF
+
+#define ANX7483_UTX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_UTX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_URX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_URX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_DRX1_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+#define ANX7483_DRX2_PORT_CFG0_REG_DEFAULT ANX7483_CFG0_DEF
+
+#define ANX7483_UTX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_UTX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_URX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_URX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_DRX1_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+#define ANX7483_DRX2_PORT_CFG1_REG_DEFAULT ANX7483_CFG1_DEF
+
+#define ANX7483_UTX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_UTX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_URX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_URX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_DRX1_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+#define ANX7483_DRX2_PORT_CFG2_REG_DEFAULT ANX7483_CFG2_DEF
+
+#define ANX7483_UTX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_UTX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_URX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_URX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DRX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DRX2_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DTX1_PORT_CFG3_REG_DEFAULT 0x02
+#define ANX7483_DTX2_PORT_CFG3_REG_DEFAULT 0x02
+
+#define ANX7483_UTX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_UTX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_URX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_URX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DRX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DRX2_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DTX1_PORT_CFG4_REG_DEFAULT 0x62
+#define ANX7483_DTX2_PORT_CFG4_REG_DEFAULT 0x62
+
+#define ANX7483_REG_MAX (ANX7483_DRX1_PORT_CFG4_REG + 1)
+
+/* Constant configuration of the emulator */
+struct anx7483_emul_cfg {
+	const struct i2c_common_emul_cfg common;
+};
+
+struct anx7483_emul_data {
+	struct i2c_common_emul_data common;
+
+	uint8_t regs[ANX7483_REG_MAX];
+};
+
+int anx7483_emul_get_reg(const struct emul *emulator, int reg, uint8_t *val);
+int anx7483_emul_set_reg(const struct emul *emulator, int reg, uint8_t val);
+
+void anx7483_emul_reset(const struct emul *emul);
+
+#endif /* __EMUL_ANX7483_H */
diff --git a/zephyr/test/drivers/Kconfig b/zephyr/test/drivers/Kconfig
index cf24966beb..7ac5a297c0 100644
--- a/zephyr/test/drivers/Kconfig
+++ b/zephyr/test/drivers/Kconfig
@@ -162,9 +162,21 @@ config LINK_TEST_SUITE_USBC_SVDM_DFP_ONLY
 	bool "Link and test the usbc_svdm_dfp_only tests"
 
 config LINK_TEST_SUITE_USBC_RETIMER
-	bool "Link and test the usbc_retimer tests"
+	bool "Link the USBC retimer tests"
+
+config LINK_TEST_SUITE_USBC_RETIMER_ANX7483
+	bool "Link and test the ANX7484 tests"
+	select LINK_TEST_SUITE_USBC_RETIMER
+	select PLATFORM_EC_USBC_RETIMER_ANX7483
+	help
+	  Include the ANX7483 test suite in the binary.
+
+config LINK_TEST_SUITE_USBC_RETIMER_PS8811
+	bool "Link and test the PS8811 tests"
+	select LINK_TEST_SUITE_USBC_RETIMER
+	select PLATFORM_EC_USBC_RETIMER_PS8811
 	help
-	  Include the usbc_retimer test suite in the binary.
+	  Include the PS8811 test suite in the binary.
 
 config LINK_TEST_SUITE_USBC_TBT_MODE
 	bool "Link and test the usbc_tbt_mode tests"
diff --git a/zephyr/test/drivers/boards/native_posix.overlay b/zephyr/test/drivers/boards/native_posix.overlay
index 561f2cd311..442a07e5dc 100644
--- a/zephyr/test/drivers/boards/native_posix.overlay
+++ b/zephyr/test/drivers/boards/native_posix.overlay
@@ -897,6 +897,11 @@
 			ls-en-pin = <&usb_c1_ls_en>;
 		};
 
+		anx7483_emul: anx7483_emul@3e {
+			compatible = "cros,anx7483-emul", "analogix,anx7483";
+			reg = <0x3e>;
+		};
+
 		ps8811_emul: ps8811_emul@72 {
 			compatible = "cros,ps8811-emul";
 			reg = <0x72>;
diff --git a/zephyr/test/drivers/testcase.yaml b/zephyr/test/drivers/testcase.yaml
index 164ca61801..7f1d71fca2 100644
--- a/zephyr/test/drivers/testcase.yaml
+++ b/zephyr/test/drivers/testcase.yaml
@@ -320,10 +320,12 @@ tests:
   drivers.usbc_ppc:
     extra_configs:
       - CONFIG_LINK_TEST_SUITE_USBC_PPC=y
+  drivers.usbc_retimer.anx7483:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483=y
   drivers.usbc_retimer.ps8811:
     extra_configs:
-      - CONFIG_LINK_TEST_SUITE_USBC_RETIMER=y
-      - CONFIG_PLATFORM_EC_USBC_RETIMER_PS8811=y
+      - CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811=y
   drivers.usbc_svdm_dfp_only:
     extra_args: CONF_FILE="prj.conf;usbc_svdm_dfp_only/prj.conf"
                 DTC_OVERLAY_FILE="usbc_svdm_dfp_only/boards/native_posix.overlay"
diff --git a/zephyr/test/drivers/usbc_retimer/CMakeLists.txt b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt
index b67b309400..5c3253328d 100644
--- a/zephyr/test/drivers/usbc_retimer/CMakeLists.txt
+++ b/zephyr/test/drivers/usbc_retimer/CMakeLists.txt
@@ -2,4 +2,5 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-target_sources_ifdef(CONFIG_EMUL_PS8811 app PRIVATE src/ps8811.c)
+target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_ANX7483 app PRIVATE src/anx7483.c)
+target_sources_ifdef(CONFIG_LINK_TEST_SUITE_USBC_RETIMER_PS8811 app PRIVATE src/ps8811.c)
diff --git a/zephyr/test/drivers/usbc_retimer/src/anx7483.c b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
new file mode 100644
index 0000000000..727bc3d435
--- /dev/null
+++ b/zephyr/test/drivers/usbc_retimer/src/anx7483.c
@@ -0,0 +1,1287 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/retimer/anx7483.h"
+#include "driver/retimer/anx7483_public.h"
+#include "emul/retimer/emul_anx7483.h"
+#include "i2c.h"
+#include "power.h"
+#include "usb_mux.h"
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#define ANX7483_EMUL EMUL_DT_GET(DT_NODELABEL(anx7483_emul))
+
+int anx7483_init(const struct usb_mux *me);
+int anx7483_set(const struct usb_mux *me, mux_state_t mux_state,
+		bool *ack_required);
+int anx7483_get(const struct usb_mux *me, mux_state_t *mux_state);
+int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val);
+int anx7483_write(const struct usb_mux *me, uint8_t reg, uint8_t val);
+
+static struct usb_mux mux = {
+	.i2c_port = I2C_PORT_NODELABEL(i2c3),
+	.i2c_addr_flags = 0x3e,
+};
+
+/* Helper functions to make tests clearer. */
+static int anx7483_emul_test_get_reg(int reg, uint8_t *val)
+{
+	return anx7483_emul_get_reg(ANX7483_EMUL, reg, val);
+}
+
+static int anx7483_emul_test_set_reg(int reg, uint8_t val)
+{
+	return anx7483_emul_set_reg(ANX7483_EMUL, reg, val);
+}
+
+static int anx7483_i2c_read(int reg, int *data)
+{
+	return anx7483_read(&mux, reg, data);
+}
+
+static int anx7483_i2c_write(int reg, int data)
+{
+	return anx7483_write(&mux, reg, data);
+}
+
+static void anx7483_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	/* Ensure the ANX7483 is on. */
+	power_set_state(POWER_S0);
+}
+
+ZTEST_SUITE(anx7483, NULL, NULL, anx7483_before, NULL, NULL);
+
+/* Verify that the reset values for all registers are correct. */
+ZTEST(anx7483, test_emul_reset)
+{
+	uint8_t val;
+	int rv;
+
+	rv = anx7483_emul_test_get_reg(ANX7483_LFPS_TIMER_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_LFPS_TIMER_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_AUX_SNOOPING_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG0_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG0_REG_DEFAULT);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG1_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG1_REG_DEFAULT);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG2_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG2_REG_DEFAULT);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG3_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG3_REG_DEFAULT);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_UTX2_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_URX2_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX1_PORT_CFG4_REG_DEFAULT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_DRX2_PORT_CFG4_REG_DEFAULT);
+}
+
+/* Test the ANX7483 driver's initialization function. */
+ZTEST(anx7483, test_init)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_init(&mux);
+	zexpect_ok(rv);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_true(val & ANX7483_CTRL_REG_EN);
+}
+
+/*
+ * Test the ANX7483 driver's anx7483_set_eq, function  which sets the
+ * equalization for a pin.
+ */
+
+ZTEST(anx7483, test_set_eq)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_UTX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_UTX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_URX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_URX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_DRX1, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	rv = anx7483_set_eq(&mux, ANX7483_PIN_DRX2, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG0_EQ_SHIFT) & 0xf,
+		      ANX7483_EQ_SETTING_12_5DB);
+
+	/* Test invalid pin. */
+	rv = anx7483_set_eq(&mux, 0xff, ANX7483_EQ_SETTING_12_5DB);
+	zexpect_not_equal(rv, 0);
+}
+
+/*
+ * Test the ANX7483 driver's anx7483_set_fg, function  which sets the flat gain
+ * for a pin.
+ */
+ZTEST(anx7483, test_set_fg)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX1, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	rv = anx7483_set_fg(&mux, ANX7483_PIN_DRX2, ANX7483_FG_SETTING_1_2DB);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal((val >> ANX7483_CFG2_FG_SHIFT) & 0x3,
+		      ANX7483_FG_SETTING_1_2DB);
+
+	/* Test invalid pin. */
+	rv = anx7483_set_fg(&mux, 0xff, ANX7483_FG_SETTING_1_2DB);
+	zexpect_not_equal(rv, 0);
+}
+
+/* Validate that accessing the emulator's registers through I2C works. */
+ZTEST(anx7483, test_emul_registers_rw)
+{
+	int rv;
+	uint8_t expected;
+	int val;
+
+	expected = (uint8_t)(ANX7483_LFPS_TIMER_REG_RESERVED_MASK &
+			     ANX7483_LFPS_TIMER_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_LFPS_TIMER_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_LFPS_TIMER_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_LFPS_TIMER_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK &
+			     ANX7483_ANALOG_STATUS_CTRL_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_ANALOG_STATUS_CTRL_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK &
+			     ANX7483_ENABLE_EQ_FLAT_SWING_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_ENABLE_EQ_FLAT_SWING_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_ENABLE_EQ_FLAT_SWING_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK &
+			     ANX7483_AUX_SNOOPING_CTRL_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_AUX_SNOOPING_CTRL_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_AUX_SNOOPING_CTRL_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG0 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG0_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG0_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG1 */
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG1_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG2 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG2_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG2_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG3 */
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = 0xff;
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG3_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* CFG4 */
+	expected = (uint8_t)(ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_UTX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_UTX2_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_UTX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_URX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_URX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_DRX1_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX1_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	expected = (uint8_t)(ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK &
+			     ANX7483_DRX2_PORT_CFG4_REG_DEFAULT);
+	expected |= (uint8_t)(~ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK);
+	rv = anx7483_i2c_write(ANX7483_DRX2_PORT_CFG4_REG, expected);
+	zexpect_ok(rv);
+	rv = anx7483_i2c_read(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_equal(val, expected);
+
+	/* Ensure that reading/writing a non-existent register fails. */
+	rv = anx7483_i2c_read(0xff, &val);
+	zexpect_not_equal(rv, 0);
+	rv = anx7483_i2c_write(0xff, 0xff);
+	zexpect_not_equal(rv, 0);
+}
+
+/* Test that the ANX7483 driver correctly reports its state. */
+ZTEST(anx7483, test_mux_state_get)
+{
+	int rv;
+	uint8_t val;
+	mux_state_t state;
+
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	val |= ANX7483_CTRL_USB_EN;
+	val |= ANX7483_CTRL_DP_EN;
+	val |= ANX7483_CTRL_FLIP_EN;
+	rv = anx7483_emul_test_set_reg(ANX7483_ANALOG_STATUS_CTRL_REG, val);
+	zexpect_ok(rv);
+
+	rv = anx7483_get(&mux, &state);
+	zexpect_ok(rv);
+	zexpect_true(val & USB_PD_MUX_USB_ENABLED);
+	zexpect_true(val & USB_PD_MUX_DP_ENABLED);
+	zexpect_true(val & USB_PD_MUX_POLARITY_INVERTED);
+}
+
+/* Test that the ANX7483 driver correctly sets the mux state. */
+ZTEST(anx7483, test_mux_state_set)
+{
+	int rv;
+	uint8_t val;
+	bool ack_required;
+
+	rv = anx7483_set(&mux,
+			 USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
+				 USB_PD_MUX_POLARITY_INVERTED,
+			 &ack_required);
+	zexpect_ok(rv);
+	rv = anx7483_emul_test_get_reg(ANX7483_ANALOG_STATUS_CTRL_REG, &val);
+	zexpect_ok(rv);
+	zexpect_true(val & ANX7483_CTRL_REG_EN);
+	zexpect_true(val & ANX7483_CTRL_USB_EN);
+	zexpect_true(val & ANX7483_CTRL_DP_EN);
+	zexpect_true(val & ANX7483_CTRL_FLIP_EN);
+}
+
+/* Validates that writing to a reserved register returns an error. */
+ZTEST(anx7483, test_emul_reserved)
+{
+	int rv;
+
+	rv = anx7483_emul_test_set_reg(ANX7483_LFPS_TIMER_REG,
+				       ANX7483_LFPS_TIMER_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_ANALOG_STATUS_CTRL_REG,
+		ANX7483_ANALOG_STATUS_CTRL_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_ENABLE_EQ_FLAT_SWING_REG,
+		ANX7483_ENABLE_EQ_FLAT_SWING_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_AUX_SNOOPING_CTRL_REG,
+		ANX7483_AUX_SNOOPING_CTRL_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG0_REG,
+		ANX7483_UTX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG0_REG,
+		ANX7483_UTX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG0_REG,
+		ANX7483_URX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG0_REG,
+		ANX7483_URX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG0_REG,
+		ANX7483_DRX1_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG0_REG,
+		ANX7483_DRX2_PORT_CFG0_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG2_REG,
+		ANX7483_UTX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG2_REG,
+		ANX7483_UTX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG2_REG,
+		ANX7483_URX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG2_REG,
+		ANX7483_URX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG2_REG,
+		ANX7483_DRX1_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG2_REG,
+		ANX7483_DRX2_PORT_CFG2_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX1_PORT_CFG4_REG,
+		ANX7483_UTX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_UTX2_PORT_CFG4_REG,
+		ANX7483_UTX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX1_PORT_CFG4_REG,
+		ANX7483_URX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_URX2_PORT_CFG4_REG,
+		ANX7483_URX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX1_PORT_CFG4_REG,
+		ANX7483_DRX1_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+
+	rv = anx7483_emul_test_set_reg(
+		ANX7483_DRX2_PORT_CFG4_REG,
+		ANX7483_DRX2_PORT_CFG4_REG_RESERVED_MASK);
+	zexpect_not_equal(rv, 0);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * USB. The register values should match those in the anx7483_usb_enabled struct
+ * within the driver.
+ */
+ZTEST(anx7483, test_tuning_usb)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_USB_ENABLED);
+	zexpect_ok(rv);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_OUT);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * DisplayPort. The register values should match those in the anx7483_dp_enabled
+ * struct within the driver.
+ */
+ZTEST(anx7483, test_tuning_dp)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DP_ENABLED);
+	zexpect_ok(rv);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * dock mode in a non-flipped state. The register values should match those in
+ * the anx7483_dock_noflip struct within the driver.
+ */
+ZTEST(anx7483, test_tuning_dock_noflip)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_default_tuning(&mux, USB_PD_MUX_DOCK);
+	zexpect_ok(rv);
+
+	/* Corresponds to anx7483_dock_noflip. */
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+}
+
+/*
+ * Tests that the ANX7483 driver correctly configures the default tuning for
+ * dock mode in a flipped state. The register values should match those in
+ * the anx7483_dock_flip struct within the driver.
+ */
+ZTEST(anx7483, test_tuning_dock_flip)
+{
+	int rv;
+	uint8_t val;
+
+	rv = anx7483_set_default_tuning(
+		&mux, USB_PD_MUX_DOCK | USB_PD_MUX_POLARITY_INVERTED);
+	zexpect_ok(rv);
+
+	/* CFG0 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG0_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG0_DEF);
+
+	/* CFG1 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG1_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG1_DEF);
+
+	/* CFG2 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG2_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG2_DEF);
+
+	/* CFG3 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_100Ohm_IN);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG3_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG3_90Ohm_IN);
+
+	/* CFG4 */
+	rv = anx7483_emul_test_get_reg(ANX7483_URX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_URX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DRX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_ENABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_UTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX1_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+
+	rv = anx7483_emul_test_get_reg(ANX7483_DTX2_PORT_CFG4_REG, &val);
+	zexpect_ok(rv);
+	zexpect_equal(val, ANX7483_CFG4_TERM_DISABLE);
+}