diff options
| author | mike <mike5@huaqin.corp-partner.google.com> | 2023-03-15 17:53:46 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-03-20 08:28:13 +0000 |
| commit | 5c098877b2f7f8add7e134bcd82c07b8969d68fd (patch) | |
| tree | e18c1c40fe7d7302aae64b641adb909e0965248d | |
| parent | ba192f443638aa8834324ea8ef06f2f3c273bc61 (diff) | |
| download | chrome-ec-5c098877b2f7f8add7e134bcd82c07b8969d68fd.tar.gz | |
Geralt: Enable CONFIG_IT83XX_TUNE_CC_PHY
Enable cc tune function to pass cc eye test
BUG=b:270906647
BRANCH=none
TEST=test geralt proto board C0 & C1 port cc
eye test pass.
Change-Id: Ie35517ba3e1fac95cd193eed64241972824c64da
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4339656
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Ganxiang Wang <wangganxiang@huaqin.corp-partner.google.com>
| -rw-r--r-- | util/config_allowed.txt | 1 | ||||
| -rw-r--r-- | zephyr/Kconfig.usbc | 8 | ||||
| -rw-r--r-- | zephyr/program/geralt/program.conf | 1 | ||||
| -rw-r--r-- | zephyr/shim/include/config_chip.h | 5 |
4 files changed, 14 insertions, 1 deletions
diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 4f46279f1e..a6e2b823b4 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -539,7 +539,6 @@ CONFIG_IT83XX_HARD_RESET_BY_GPG1 CONFIG_IT83XX_I2C_CMD_QUEUE CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM CONFIG_IT83XX_SMCLK2_ON_GPC7 -CONFIG_IT83XX_TUNE_CC_PHY CONFIG_IT83XX_VCC_1P8V CONFIG_IT83XX_VCC_3P3V CONFIG_IT8XXX2_MUL_WORKAROUND diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc index 6dcf03335c..9248b429ee 100644 --- a/zephyr/Kconfig.usbc +++ b/zephyr/Kconfig.usbc @@ -245,6 +245,14 @@ config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2 This supports up to two USB Type-C ports with Dual Role function (provider and consumer) and Fast Role Swap detection. +config PLATFORM_EC_IT83XX_TUNE_CC_PHY + bool "Enable tune cc physical parameters" + depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP + help + Enable board to tune cc physical parameters (ex.rising, falling time). + Board must define board_get_cc_tuning_parameter(enum usbpd_port port) + function. + config PLATFORM_EC_USB_PD_PULLUP int "Default source Rp value" default 1 diff --git a/zephyr/program/geralt/program.conf b/zephyr/program/geralt/program.conf index cb1c1f2435..852525672c 100644 --- a/zephyr/program/geralt/program.conf +++ b/zephyr/program/geralt/program.conf @@ -153,6 +153,7 @@ CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y CONFIG_PLATFORM_EC_USB_PD_LOGGING=y CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_IT83XX_TUNE_CC_PHY=y CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index d8ef2b04f2..bfd962de29 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -1588,6 +1588,11 @@ extern char mock_jump_data[CONFIG_PLATFORM_EC_PRESERVED_END_OF_RAM_SIZE]; #define CONFIG_USB_PD_TCPM_DRIVER_IT83XX #endif +#undef CONFIG_IT83XX_TUNE_CC_PHY +#ifdef CONFIG_PLATFORM_EC_IT83XX_TUNE_CC_PHY +#define CONFIG_IT83XX_TUNE_CC_PHY +#endif + #undef CONFIG_USB_PD_TCPM_RAA489000 #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000 #define CONFIG_USB_PD_TCPM_RAA489000 |