summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAdam Mills <adamjmills@google.com>2022-08-31 13:00:24 +1000
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-09-01 15:00:07 +0000
commit52c0eb7445ce1debfb01d1c355efb52fa7fda4e5 (patch)
treeb36f2897607bf2f06719c00eb2b822d2f8cd18ea
parenta57e1ae3adc248977c8b7b2c6fe42bc24478ce06 (diff)
downloadchrome-ec-52c0eb7445ce1debfb01d1c355efb52fa7fda4e5.tar.gz
zephyr: Fix PPC chips on the i2c nodes for herobrine variants.
Two of the herobrine variants (hoglin and villager) use different PPC chips to the other herobrine boards. To facilitate this difference between the boards, the variant specific i2c DTS files needed to be updated with the correct PPC chips. BUG=b:243759491 TEST=zmake build -a; ./twister -T zephyr/test/ BRANCH=main Signed-off-by: Adam Mills <adamjmills@google.com> Change-Id: I00748d71d458e847e141dbbfa3a1ffcf7fa63379 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3864593 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
-rw-r--r--zephyr/projects/herobrine/i2c_common.dtsi21
-rw-r--r--zephyr/projects/herobrine/i2c_evoker.dts21
-rw-r--r--zephyr/projects/herobrine/i2c_herobrine.dts21
-rw-r--r--zephyr/projects/herobrine/i2c_hoglin.dts16
-rw-r--r--zephyr/projects/herobrine/i2c_villager.dts16
5 files changed, 71 insertions, 24 deletions
diff --git a/zephyr/projects/herobrine/i2c_common.dtsi b/zephyr/projects/herobrine/i2c_common.dtsi
index 27af28cc7a..7a553b995c 100644
--- a/zephyr/projects/herobrine/i2c_common.dtsi
+++ b/zephyr/projects/herobrine/i2c_common.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -84,19 +84,6 @@
clock-frequency = <I2C_BITRATE_FAST_PLUS>;
pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
pinctrl-names = "default";
-
- ppc_port0: sn5s330@40 {
- compatible = "ti,sn5s330";
- status = "okay";
- reg = <0x40>;
- };
-
- ppc_port0_alt: syv682x@41 {
- compatible = "silergy,syv682x";
- status = "okay";
- reg = <0x41>;
- frs_en_gpio = <&gpio_usb_c0_frs_en>;
- };
};
&i2c_ctrl1 {
@@ -109,12 +96,6 @@
clock-frequency = <I2C_BITRATE_FAST_PLUS>;
pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
pinctrl-names = "default";
-
- ppc_port1: sn5s330@40 {
- compatible = "ti,sn5s330";
- status = "okay";
- reg = <0x40>;
- };
};
&i2c_ctrl2 {
diff --git a/zephyr/projects/herobrine/i2c_evoker.dts b/zephyr/projects/herobrine/i2c_evoker.dts
index c72ab99054..cab6620394 100644
--- a/zephyr/projects/herobrine/i2c_evoker.dts
+++ b/zephyr/projects/herobrine/i2c_evoker.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,19 @@
#include "i2c_common.dtsi"
&i2c1_0 {
+ ppc_port0: sn5s330@40 {
+ compatible = "ti,sn5s330";
+ status = "okay";
+ reg = <0x40>;
+ };
+
+ ppc_port0_alt: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c0_frs_en>;
+ };
+
tcpc_port0: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;
@@ -13,6 +26,12 @@
};
&i2c2_0 {
+ ppc_port1: sn5s330@40 {
+ compatible = "ti,sn5s330";
+ status = "okay";
+ reg = <0x40>;
+ };
+
tcpc_port1: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;
diff --git a/zephyr/projects/herobrine/i2c_herobrine.dts b/zephyr/projects/herobrine/i2c_herobrine.dts
index c72ab99054..cab6620394 100644
--- a/zephyr/projects/herobrine/i2c_herobrine.dts
+++ b/zephyr/projects/herobrine/i2c_herobrine.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,19 @@
#include "i2c_common.dtsi"
&i2c1_0 {
+ ppc_port0: sn5s330@40 {
+ compatible = "ti,sn5s330";
+ status = "okay";
+ reg = <0x40>;
+ };
+
+ ppc_port0_alt: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c0_frs_en>;
+ };
+
tcpc_port0: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;
@@ -13,6 +26,12 @@
};
&i2c2_0 {
+ ppc_port1: sn5s330@40 {
+ compatible = "ti,sn5s330";
+ status = "okay";
+ reg = <0x40>;
+ };
+
tcpc_port1: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;
diff --git a/zephyr/projects/herobrine/i2c_hoglin.dts b/zephyr/projects/herobrine/i2c_hoglin.dts
index 37cd7a93e1..0b97048929 100644
--- a/zephyr/projects/herobrine/i2c_hoglin.dts
+++ b/zephyr/projects/herobrine/i2c_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,13 @@
#include "i2c_common.dtsi"
&i2c1_0 {
+ ppc_port0: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c0_frs_en>;
+ };
+
tcpc_port0: ps8xxx@1b {
compatible = "parade,ps8xxx";
reg = <0x1b>;
@@ -13,6 +20,13 @@
};
&i2c2_0 {
+ ppc_port1: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c1_frs_en>;
+ };
+
tcpc_port1: ps8xxx@1b {
compatible = "parade,ps8xxx";
reg = <0x1b>;
diff --git a/zephyr/projects/herobrine/i2c_villager.dts b/zephyr/projects/herobrine/i2c_villager.dts
index c72ab99054..a56bd740ac 100644
--- a/zephyr/projects/herobrine/i2c_villager.dts
+++ b/zephyr/projects/herobrine/i2c_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -6,6 +6,13 @@
#include "i2c_common.dtsi"
&i2c1_0 {
+ ppc_port0: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c0_frs_en>;
+ };
+
tcpc_port0: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;
@@ -13,6 +20,13 @@
};
&i2c2_0 {
+ ppc_port1: syv682x@41 {
+ compatible = "silergy,syv682x";
+ status = "okay";
+ reg = <0x41>;
+ frs_en_gpio = <&gpio_usb_c1_frs_en>;
+ };
+
tcpc_port1: ps8xxx@b {
compatible = "parade,ps8xxx";
reg = <0xb>;