core: add chip-specific memory regions definition mechanism

When a chip has special/non-contiguous SRAM physical memory region,
rather than extending the generic linker file ad nauseam, define a
mechanism to declare a chip specific list of those regions.

To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS
configuration and have a memory_regions.inc with the list of regions.

The special-purpose preprocessed chip/<chip_name>/memory_regions.inc
file has one region declaration per line using the following macro:
REGION(name, attributes, start_address, size)

Each region will get a proper MEMORY entry and a section in the linker
file.
the __SECTION(region_name) helper is provided as a convenience to
declare variable in a specific region.

Note: those 'special' regions are NOT cleared at startup contrary to
.bss.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.

Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c
Reviewed-on: https://chromium-review.googlesource.com/946368
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit b42dd73603844c03b44d88a4513df330ee168496)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2723455
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>

4 files changed, 50 insertions, 0 deletions

diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index 3390a0a58f..d629a8e7fa 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -57,6 +57,12 @@ MEMORY
         ORIGIN = CONFIG_USB_RAM_BASE, \
         LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2
 #endif
+#ifdef CONFIG_CHIP_MEMORY_REGIONS
+#define REGION(name, attr, start, size) \
+    name(attr) : ORIGIN = (start), LENGTH = (size)
+#include "memory_regions.inc"
+#undef REGION
+#endif /* CONFIG_MEMORY_REGIONS */
 }
 SECTIONS
 {
@@ -365,6 +371,16 @@ SECTIONS
         *(.usb_ram.data)
     } > USB_RAM
 #endif
+#ifdef CONFIG_CHIP_MEMORY_REGIONS
+#define REGION(name, attr, start, size) \
+    .name(NOLOAD) : { \
+        __##name##_start = .; \
+        *(SORT(.name.*)) \
+    } > name
+#include "memory_regions.inc"
+#undef REGION
+#endif /* CONFIG_CHIP_MEMORY_REGIONS */
+
 #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
     /DISCARD/ : {
               *(.google)
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index a43499ab27..54087e9bd7 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -30,6 +30,12 @@ MEMORY
         ORIGIN = CONFIG_USB_RAM_BASE, \
         LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2
 #endif
+#ifdef CONFIG_CHIP_MEMORY_REGIONS
+#define REGION(name, attr, start, size) \
+    name(attr) : ORIGIN = (start), LENGTH = (size)
+#include "memory_regions.inc"
+#undef REGION
+#endif /* CONFIG_MEMORY_REGIONS */
 }
 SECTIONS
 {
@@ -242,6 +248,16 @@ SECTIONS
         *(.usb_ram.data)
     } > USB_RAM
 #endif
+#ifdef CONFIG_CHIP_MEMORY_REGIONS
+#define REGION(name, attr, start, size) \
+    .name(NOLOAD) : { \
+        __##name##_start = .; \
+        *(SORT(.name.*)) \
+    } > name
+#include "memory_regions.inc"
+#undef REGION
+#endif /* CONFIG_CHIP_MEMORY_REGIONS */
+
 #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH))
     /DISCARD/ : {
               *(.google)
diff --git a/include/config.h b/include/config.h
index 0c39ea96c6..9f2533cda9 100644
--- a/include/config.h
+++ b/include/config.h
@@ -580,6 +580,17 @@
 #undef CONFIG_TRICKLE_CHARGING
 
 /*****************************************************************************/
+
+/*
+ * The chip needs to define special SRAM memory regions as linker sections.
+ * Those regions are defined in the special-purpose preprocessed file in
+ * chip/<chip_name>/memory_regions.inc using the following macro:
+ * REGION(name, attributes, start_address, size)
+ *
+ * Note: these 'special' regions are NOT cleared at startup contrary to .bss.
+ */
+#undef CONFIG_CHIP_MEMORY_REGIONS
+
 /* Chipset config */
 
 /* AP chipset support; pick at most one */
diff --git a/include/link_defs.h b/include/link_defs.h
index 1f16399cf7..27f8f0481e 100644
--- a/include/link_defs.h
+++ b/include/link_defs.h
@@ -96,4 +96,11 @@ extern const void *__ro_end;
 extern const void *__data_start;
 extern const void *__data_end;
 
+/* Helper for special chip-specific memory sections */
+#ifdef CONFIG_CHIP_MEMORY_REGIONS
+#define __SECTION(name) __attribute__((section("." STRINGIFY(name) ".50_auto")))
+#else
+#define __SECTION(name)
+#endif /* CONFIG_MEMORY_REGIONS */
+
 #endif /* __CROS_EC_LINK_DEFS_H */