diff options
| author | Koro Chen <koro.chen@mediatek.com> | 2016-03-07 21:53:14 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-05-01 21:20:03 +0000 |
| commit | a61c79c936ce25cb929564fe8c621307c5c4f46e (patch) | |
| tree | aca4fed1a220d01eb73a952f9b1645a7e21f59df | |
| parent | b7af4532ee2daccac70399ae96f3675140f54e5f (diff) | |
| download | chrome-ec-a61c79c936ce25cb929564fe8c621307c5c4f46e.tar.gz | |
BACKPORT: elm: kionix: allow dynamic selection of SPI or I2C transport
This CL ports c9832e04f1528 to Kionix accel driver. And also enables SPI
access of Elm's base kx022.
BUG=b:27849483, b:36973851
BRANCH=cyan, ultima
TEST=manual
Reviewed-on: https://chromium-review.googlesource.com/331851
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
(cherry picked from commit f00d4621a480f12293214f14716ac33a90281ce7)
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359406
Reviewed-on: https://chromium-review.googlesource.com/409493
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit d8afbac8da1204dc52242c6f778bd6ea11577594)
Change-Id: I0c1de028c82fc62a124bb5b930a3882c4b368d71
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/489766
| -rw-r--r-- | driver/accel_kionix.c | 58 | ||||
| -rw-r--r-- | driver/accel_kionix.h | 14 |
2 files changed, 66 insertions, 6 deletions
diff --git a/driver/accel_kionix.c b/driver/accel_kionix.c index 0a3754b4dd..b715173b7e 100644 --- a/driver/accel_kionix.c +++ b/driver/accel_kionix.c @@ -17,6 +17,7 @@ #include "driver/accel_kxcj9.h" #include "i2c.h" #include "math_util.h" +#include "spi.h" #include "task.h" #include "util.h" @@ -128,7 +129,23 @@ static int find_param_index(const int eng_val, const int round_up, static int raw_read8(const int port, const int addr, const int reg, int *data_ptr) { - return i2c_read8(port, addr, reg, data_ptr); + int rv; + + if (KIONIX_IS_SPI(addr)) { +#ifdef CONFIG_SPI_ACCEL_PORT + uint8_t val; + uint8_t cmd = 0x80 | reg; + + rv = spi_transaction(&spi_devices[KIONIX_SPI_ADDRESS(addr)], + &cmd, 1, &val, 1); + if (rv == EC_SUCCESS) + *data_ptr = val; + +#endif + } else { + rv = i2c_read8(port, addr, reg, data_ptr); + } + return rv; } /** @@ -136,7 +153,39 @@ static int raw_read8(const int port, const int addr, const int reg, */ static int raw_write8(const int port, const int addr, const int reg, int data) { - return i2c_write8(port, addr, reg, data); + int rv; + + if (KIONIX_IS_SPI(addr)) { +#ifdef CONFIG_SPI_ACCEL_PORT + uint8_t cmd[2] = { reg, data }; + + rv = spi_transaction(&spi_devices[KIONIX_SPI_ADDRESS(addr)], + cmd, 2, NULL, 0); +#endif + } else { + rv = i2c_write8(port, addr, reg, data); + } + return rv; +} + +static int raw_read_multi(const int port, int addr, uint8_t reg, + uint8_t *rxdata, int rxlen) +{ + int rv; + + if (KIONIX_IS_SPI(addr)) { +#ifdef CONFIG_SPI_ACCEL_PORT + reg |= 0x80; + rv = spi_transaction(&spi_devices[KIONIX_SPI_ADDRESS(addr)], + ®, 1, rxdata, rxlen); +#endif + } else { + i2c_lock(port, 1); + rv = i2c_xfer(port, addr, ®, 1, rxdata, rxlen, + I2C_XFER_SINGLE); + i2c_lock(port, 0); + } + return rv; } /** @@ -378,10 +427,7 @@ static int read(const struct motion_sensor_t *s, vector_3_t v) /* Read 6 bytes starting at XOUT_L. */ reg = KIONIX_XOUT_L(data->variant); mutex_lock(s->mutex); - i2c_lock(s->port, 1); - ret = i2c_xfer(s->port, s->addr, ®, 1, acc, 6, - I2C_XFER_SINGLE); - i2c_lock(s->port, 0); + ret = raw_read_multi(s->port, s->addr, reg, acc, 6); mutex_unlock(s->mutex); if (ret != EC_SUCCESS) diff --git a/driver/accel_kionix.h b/driver/accel_kionix.h index e326dd3cb3..3dc7f314a4 100644 --- a/driver/accel_kionix.h +++ b/driver/accel_kionix.h @@ -44,6 +44,20 @@ struct kionix_accel_data { extern const struct accelgyro_drv kionix_accel_drv; +/* + * The addr field of motion_sensor support both SPI and I2C: + * + * +-------------------------------+---+ + * | 7 bit i2c address | 0 | + * +-------------------------------+---+ + * Or + * +-------------------------------+---+ + * | SPI device ID | 1 | + * +-------------------------------+---+ + */ +#define KIONIX_IS_SPI(_addr) ((_addr) & 1) +#define KIONIX_SPI_ADDRESS(_addr) ((_addr) >> 1) + #define KIONIX_CTRL1_REG(v) (KX022_CNTL1 + \ (v) * (KXCJ9_CTRL1 - KX022_CNTL1)) #define KIONIX_CTRL2_REG(v) (KX022_CNTL2 + \ |