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| author | Scott Collyer <scollyer@google.com> | 2021-03-04 19:07:23 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-19 17:40:06 +0000 |
| commit | f5b3331acc0dab9c72cacd7c4e40df3342991595 (patch) | |
| tree | 7cd36d25fb19531ac42ffe776850e89b610122c8 | |
| parent | aa1e4b893f3bf5961d0ea38cae52afd62ef17c98 (diff) | |
| download | chrome-ec-f5b3331acc0dab9c72cacd7c4e40df3342991595.tar.gz | |
TCPMv2: Don't enter Tx BIST mode when VBUS > VSafe5V
By spec we are only allowed to enter BIST mode when VBUS is at
vSafe5V. This CL adds a check in pe_bist_tx_entry to make sure that
BIST test mode is only entered if VBUS is at the correct level.
We compared to the expected nominal VBUS level and not the actual
measured level as not all boards will have accurate enough VBUS
measurements.
BUG=b:180957710
BRANCH=None
TEST=Verfied that quiche can pass the TDA.2.2.7 compliance test.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Icc2e5ff6c32374c89490e5bea79af2c4517ea295
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738397
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774589
Tested-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
| -rw-r--r-- | common/usbc/usb_pe_drp_sm.c | 19 | ||||
| -rw-r--r-- | include/usb_pd.h | 1 |
2 files changed, 20 insertions, 0 deletions
diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index 6ab4a9cb17..e57acc173e 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -4908,9 +4908,28 @@ static void pe_bist_tx_entry(int port) { uint32_t *payload = (uint32_t *)rx_emsg[port].buf; uint8_t mode = BIST_MODE(payload[0]); + int vbus_mv; + int ibus_ma; print_current_state(port); + /* Get the current nominal VBUS value */ + if (pe[port].power_role == PD_ROLE_SOURCE) { + const uint32_t *src_pdo; + + dpm_get_source_pdo(&src_pdo, port); + pd_extract_pdo_power(src_pdo[pe[port].requested_idx - 1], + &ibus_ma, &vbus_mv); + } else { + vbus_mv = pe[port].supply_voltage; + } + + /* If VBUS is not at vSafe5V, then don't enter BIST test mode */ + if (vbus_mv != PD_V_SAFE5V_NOM) { + pe_set_ready_state(port); + return; + } + if (mode == BIST_CARRIER_MODE_2) { /* * PE_BIST_Carrier_Mode embedded here. diff --git a/include/usb_pd.h b/include/usb_pd.h index c8f91fbed2..3526adf716 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -275,6 +275,7 @@ enum pd_rx_errors { /* Voltage thresholds in mV (Table 7-24, PD 3.0 Version 2.0 Spec) */ #define PD_V_SAFE0V_MAX 800 #define PD_V_SAFE5V_MIN 4750 +#define PD_V_SAFE5V_NOM 5000 #define PD_V_SAFE5V_MAX 5500 /* USB Type-C voltages in mV (Table 4-3, USB Type-C Release 2.0 Spec) */ |