diff options
author | Jun Lin <CHLin56@nuvoton.com> | 2021-03-17 11:48:13 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-03-19 17:40:18 +0000 |
commit | 07da1682d819ecad667ba0c05bc44e7fe52601a1 (patch) | |
tree | 6ad6457c706592538df5dd88ab20dc295359efb9 | |
parent | 538b3c9eb9200b4c4732e1c2565c96d8e69d6632 (diff) | |
download | chrome-ec-07da1682d819ecad667ba0c05bc44e7fe52601a1.tar.gz |
npcx: eSPI: add a config to reset SLP_Sx VW when eSPI_RST asserts
It was observed that in byra, when the "apshutdown" console command is
executed, the power state of EC is messed up. This was caused by the
SLP_Sx virtual wire is not updated due to the ungraceful global reset.
This CL adds a config option to let npcx EC reset SLP_Sx VW when
eSPI_RST is asserted.
Note: don't enable this config if the platform implements deep Sx entry
(e.g. KBL) for the reason per Intel eSPI spec. (scenario 3 in Table 7):
These pins retain state (0 or 1) until PCH/SoC exits Deep-Sx and PMC
sends a VW message to the EC with the new states for these pins.
BRANCH=none
BUG=b:179977907
TEST=pass "make buildall"
TEST=With the config defined, see the SLP_S4 virtual wire reset when
eSPI_RST is asserted.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I413b3d211537295b32c49b6e4a1797e48a26ec5f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2766428
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774592
Tested-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
-rw-r--r-- | chip/npcx/espi.c | 4 | ||||
-rw-r--r-- | include/config.h | 31 |
2 files changed, 35 insertions, 0 deletions
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 9073838bd6..2ab2606ecc 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -62,7 +62,11 @@ struct vw_event_t { /* Default settings of VWEVMS registers (Please refer Table.43/44) */ static const struct vwevms_config_t espi_in_list[] = { /* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ +#ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST + {0x02, 1, 0, 1, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ +#else {0x02, 1, 0, 0, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ +#endif {0x03, 1, 0, 1, 1}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ {0x07, 1, 1, 1, 1}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ {0x41, 1, 0, 1, 1}, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ diff --git a/include/config.h b/include/config.h index 07c333deab..aefb3a4bdd 100644 --- a/include/config.h +++ b/include/config.h @@ -2923,6 +2923,37 @@ */ #undef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP +/* + * Background information (from Intel eSPI Compatibility Specification): + * eSPI_Reset# may be asserted as part of: + * (1) a normal Deep-Sx entry: + * A normal eSPI_Reset# assertion is preceded by {Host,OOB}_Reset_Warn/Ack + * handshakes (using tunneled VWs) between the PCH/SoC and the EC/BMC. + * The eSPI Specification states that the SLP_* signals are reset based on + * eSPI_Reset#. However, for platforms that support Deep Sleep Well (DSW), + * the SLP_{S3,S4,S5,LAN,WLAN}# signals reside in the DSW power well and are + * reset by DSW_PWROK. + * In PCH/SoC, the states of these pins will be communicated to the EC/BMC + * as Virtual Wires over the eSPI interface. As a result, the EC/BMC needs + * to handle/maintain these pins' states during Deep-Sx. + * + * (2) a Global Reset event: + * It could happen in the middle of an on-going eSPI transaction, which is + * immediately truncated. All tunneled VWs, including + * SLP_{S3,S4,S5,LAN,WLAN}#, are returned to their default reset default + * state upon entry into Global Reset. Note that in the case of a Global + * Reset event, eSPI Virtual Wire messages deasserting the states of these + * wires will not be issued by the eSPI-MC. The eSPI Slave device is + * responsible for resetting the states of all its VWs at the appropriate + * platform reset events. + * + * Enable this config to reset SLP* VW when eSPI_RST is asserted for the Global + * Reset event case. + * Don't enable this config if the platform implements the Deep-Sx entry as EC + * needs to maintain these pins' states per request. + */ +#undef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST + /* Base address of low power RAM. */ #undef CONFIG_LPRAM_BASE |