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| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-01-15 11:36:49 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-22 17:51:59 +0000 |
| commit | 4fb279799bd7c3f92fdf298d33c35f7a29ad0550 (patch) | |
| tree | 27dc15cef091dc59717989c627851c81bb2df99c | |
| parent | 22c91115c6cf38db60410a2ee1bbeb6fc082223d (diff) | |
| download | chrome-ec-4fb279799bd7c3f92fdf298d33c35f7a29ad0550.tar.gz | |
zephyr: power: add shim option for S0ix
Add a shim option for enabling S0ix and host sleep tracking.
BUG=b:177609422
BRANCH=none
TEST=power sequence kohaku
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I2a41ec509339879c6a372bdc7d2d6d2e2bb651ae
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2633821
Reviewed-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | zephyr/CMakeLists.txt | 2 | ||||
| -rw-r--r-- | zephyr/Kconfig.powerseq | 15 | ||||
| -rw-r--r-- | zephyr/shim/include/config_chip.h | 10 |
3 files changed, 27 insertions, 0 deletions
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 47ca1af9ef..5b63aca395 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -125,6 +125,8 @@ zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL "${PLATFORM_EC}/common/power_button_x86.c" "${PLATFORM_EC}/power/intel_x86.c") +zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP + "${PLATFORM_EC}/power/host_sleep.c") zephyr_sources_ifdef(CONFIG_PLATFORM_EC_TIMER "${PLATFORM_EC}/common/timer.c") zephyr_sources_ifdef(CONFIG_PLATFORM_EC_USB_CHARGER diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq index 9481915644..1b7930f3d2 100644 --- a/zephyr/Kconfig.powerseq +++ b/zephyr/Kconfig.powerseq @@ -15,6 +15,13 @@ menuconfig PLATFORM_EC_POWERSEQ if PLATFORM_EC_POWERSEQ +config PLATFORM_EC_POWERSEQ_HOST_SLEEP + bool "Track host sleep states" + help + Enable EC code to track the AP sleep states. This is + required for S0ix support on Intel platforms, and optional + for boards without S0ix support. + menuconfig PLATFORM_EC_POWERSEQ_INTEL bool "Enable shimming common Intel power sequencing code" depends on AP_X86_INTEL @@ -53,6 +60,14 @@ config PLATFORM_EC_POWERSEQ_RTC_RESET gpio_map.h, which can be used to reset the AP's RTC when set high. +config PLATFORM_EC_POWERSEQ_S0IX + bool "Enable S0ix sleep states" + select PLATFORM_EC_POWERSEQ_HOST_SLEEP + help + Enable the CONFIG_POWER_S0IX platform/ec configuration + option, Intel's low-power idle sleep state, also known as + "modern sleep". + config PLATFORM_EC_POWERSEQ_COMETLAKE bool "Use common Comet Lake code for power sequencing" depends on AP_X86_INTEL_CML diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index e335010fa3..1931f155d0 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -164,6 +164,11 @@ enum battery_type { #define CONFIG_CHIPSET_CPU_PROCHOT_ACTIVE_LOW #endif +#undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#ifdef CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#endif + #ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY #define CONFIG_CHIPSET_X86_RSMRST_DELAY #endif @@ -184,6 +189,11 @@ enum battery_type { #define CONFIG_POWER_PP5000_CONTROL #endif +#undef CONFIG_POWER_S0IX +#ifdef CONFIG_PLATFORM_EC_POWERSEQ_S0IX +#define CONFIG_POWER_S0IX +#endif + #undef CONFIG_FAKE_SHMEM #ifdef CONFIG_ARCH_POSIX #define CONFIG_FAKE_SHMEM |