driver: rt1715 : Improve noise rejection

Adjust CC noise rejection parameters based on CC voltage
after getting CC levels and before setting polarity.
Adjust electrical parameters to Richtek-recommended values.

BUG=b:173023411, b:171461736
BRANCH=cros/main
TEST=Pass TDA.2.1.2.1 BMC PHY RX BUSIDL with Volteer+RT1715

Change-Id: I70990e59d15cb59e868d51852dec27100f8d732c
Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2599786
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
Tested-by: Abe Levkoy <alevkoy@chromium.org>

2 files changed, 172 insertions, 19 deletions

diff --git a/driver/tcpm/rt1715.c b/driver/tcpm/rt1715.c
index 90aa28138a..db5e7a929d 100644
--- a/driver/tcpm/rt1715.c
+++ b/driver/tcpm/rt1715.c
@@ -1,8 +1,7 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-
 /* Richtek RT1715 Type-C port controller */
 
 #include "common.h"
@@ -11,52 +10,153 @@
 #include "tcpm/tcpm.h"
 #include "timer.h"
 #include "usb_pd.h"
+#include "usb_pd_tcpm.h"
 
 #ifndef CONFIG_USB_PD_TCPM_TCPCI
 #error "RT1715 is using a standard TCPCI interface"
 #error "Please upgrade your board configuration"
 #endif
 
+static int rt1715_polarity[CONFIG_USB_PD_PORT_MAX_COUNT];
+
 static int rt1715_enable_ext_messages(int port, int enable)
 {
 	return tcpc_update8(port, RT1715_REG_VENDOR_5,
-			    RT1715_REG_VENDOR_5_ENEXTMSG,
-			    enable ? MASK_SET : MASK_CLR);
+		  RT1715_REG_VENDOR_5_ENEXTMSG,
+		  enable ? MASK_SET : MASK_CLR);
 }
 
 static int rt1715_tcpci_tcpm_init(int port)
 {
 	int rv;
-
 	/* RT1715 has a vendor-defined register reset */
 	rv = tcpc_update8(port, RT1715_REG_VENDOR_7,
-			  RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
+		  RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
 	if (rv)
 		return rv;
 
 	msleep(10);
+
 	rv = tcpc_update8(port, RT1715_REG_VENDOR_5,
-			  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
+		  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
 	if (rv)
 		return rv;
 
 	if (IS_ENABLED(CONFIG_USB_PD_REV30))
 		rt1715_enable_ext_messages(port, 1);
+
+	rv = tcpc_write(port, RT1715_REG_I2CRST_CTRL,
+		  (RT1715_REG_I2CRST_CTRL_EN |
+		  RT1715_REG_I2CRST_CTRL_TOUT_200MS));
+	if (rv)
+		return rv;
+
+	/*
+	 * Set tTCPCFilter (CC debounce time) to 400 us
+	 * (min 250 us, max 500 us).
+	 */
+	rv = tcpc_write(port, RT1715_REG_TTCPC_FILTER,
+		  RT1715_REG_TTCPC_FILTER_400US);
+	if (rv)
+		return rv;
+
+	rv = tcpc_write(port, RT1715_REG_DRP_TOGGLE_CYCLE,
+		  RT1715_REG_DRP_TOGGLE_CYCLE_76MS);
+	if (rv)
+		return rv;
+
+	/* PHY control */
+	/* Set PHY control registers to Richtek recommended values */
+	rv = tcpc_write(port, RT1715_REG_PHY_CTRL1,
+		  (RT1715_REG_PHY_CTRL1_ENRETRY |
+		  RT1715_REG_PHY_CTRL1_TRANSCNT_7 |
+		  RT1715_REG_PHY_CTRL1_TRXFILTER_125NS));
+	if (rv)
+		return rv;
+
+	/* Set PHY control registers to Richtek recommended values */
+	rv = tcpc_write(port, RT1715_REG_PHY_CTRL2,
+		  RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US);
+	if (rv)
+		return rv;
+
 	return tcpci_tcpm_init(port);
 }
 
+/*
+ * Selects the CC PHY noise filter voltage level according to the current
+ * CC voltage level.
+ *
+ * @param cc_level The CC voltage level for the port's current role
+ * @return EC_SUCCESS if writes succeed; failure code otherwise
+ */
+static inline int rt1715_init_cc_params(int port, int cc_level)
+{
+	int rv, en, sel;
+
+	if (cc_level == TYPEC_CC_VOLT_RP_DEF) {
+		/* RXCC threshold : 0.55V */
+		en = RT1715_REG_BMCIO_RXDZEN_DISABLE;
+
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
+		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
+	} else {
+		/* RD threshold : 0.35V & RP threshold : 0.75V */
+		en = RT1715_REG_BMCIO_RXDZEN_ENABLE;
+
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
+		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
+	}
+
+	rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZEN, en);
+	if (!rv)
+		rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZSEL, sel);
+
+	return rv;
+}
+
+static int rt1715_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+	enum tcpc_cc_voltage_status *cc2)
+{
+	int rv;
+
+	rv = tcpci_tcpm_get_cc(port, cc1, cc2);
+	if (rv)
+		return rv;
+
+	return rt1715_init_cc_params(port, rt1715_polarity[port] ? *cc2 : *cc1);
+}
+
+static int rt1715_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
+	int rv;
+	enum tcpc_cc_voltage_status cc1, cc2;
+
+	rt1715_polarity[port] = polarity;
+
+	rv = tcpci_tcpm_get_cc(port, &cc1, &cc2);
+	if (rv)
+		return rv;
+
+	rv = rt1715_init_cc_params(port, polarity ? cc2 : cc1);
+	if (rv)
+		return rv;
+
+	return tcpci_tcpm_set_polarity(port, polarity);
+}
+
 const struct tcpm_drv rt1715_tcpm_drv = {
 	.init = &rt1715_tcpci_tcpm_init,
 	.release = &tcpci_tcpm_release,
-	.get_cc = &tcpci_tcpm_get_cc,
+	.get_cc = &rt1715_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
 	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
 	.select_rp_value = &tcpci_tcpm_select_rp_value,
 	.set_cc = &tcpci_tcpm_set_cc,
-	.set_polarity = &tcpci_tcpm_set_polarity,
+	.set_polarity = &rt1715_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable   = &tcpci_tcpm_sop_prime_enable,
 #endif
 	.set_vconn = &tcpci_tcpm_set_vconn,
 	.set_msg_header = &tcpci_tcpm_set_msg_header,
diff --git a/driver/tcpm/rt1715.h b/driver/tcpm/rt1715.h
index dd259b9f70..334ab8f522 100644
--- a/driver/tcpm/rt1715.h
+++ b/driver/tcpm/rt1715.h
@@ -1,20 +1,73 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-
 /* Richtek RT1715 Type-C port controller */
-
 #ifndef __CROS_EC_USB_PD_TCPM_RT1715_H
 #define __CROS_EC_USB_PD_TCPM_RT1715_H
 
-#include "driver/tcpm/rt1715_public.h"
+/* I2C interface */
+#define RT1715_I2C_ADDR_FLAGS                   0x4E
+
+#define RT1715_VENDOR_ID                        0x29CF
+
+#define RT1715_REG_VENDOR_7                     0xA0
+#define RT1715_REG_VENDOR_7_SOFT_RESET          BIT(0)
+
+#define RT1715_REG_PHY_CTRL1                    0x80
+/* Wait for tReceive before retrying transmit in response to a bad GoodCRC */
+#define RT1715_REG_PHY_CTRL1_ENRETRY            BIT(7)
+/*
+ * Bit 6:4 <TRANSCNT>: Consider CC to be idle if there are 7 or fewer BMC
+ * transients observed in <46.67us>
+ */
+#define RT1715_REG_PHY_CTRL1_TRANSCNT_7         0x70
+/*
+ * Bit 1:0 <TRXFilter>: RX filter to make sure the stable received PD message.
+ * default value is 01b
+ * The debounce time is (register value + 2) * 41.67ns
+ */
+#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS    0x01
+#define RT1715_REG_PHY_CTRL2                    0x81
+/*
+ * Decrease the time that the PHY will wait for a second transition to detect
+ * a BMC-encoded 1 bit from 2.67 us to 2.25 us.
+ * Timeout = register value * .04167 us.
+ */
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US   54
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US	60
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US	62
+
+#define RT1715_REG_BMCIO_RXDZSEL                0x93
+#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA   BIT(7)
+#define RT1715_REG_BMCIO_RXDZSEL_SEL            BIT(0)
+
+#define RT1715_REG_VENDOR_5                     0x9B
+#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF        BIT(5)
+#define RT1715_REG_VENDOR_5_ENEXTMSG            BIT(4)
+
+#define RT1715_REG_I2CRST_CTRL                  0x9E
+/* I2C reset : (val + 1) * 12.5ms */
+#define RT1715_REG_I2CRST_CTRL_TOUT_200MS       0x0F
+#define RT1715_REG_I2CRST_CTRL_TOUT_150MS       0x0B
+#define RT1715_REG_I2CRST_CTRL_TOUT_100MS       0x07
+#define RT1715_REG_I2CRST_CTRL_EN               BIT(7)
+
+
+#define RT1715_REG_TTCPC_FILTER                 0xA1
+#define RT1715_REG_TTCPC_FILTER_400US           0x0F
+
+#define RT1715_REG_DRP_TOGGLE_CYCLE             0xA2
+/* DRP Duty : (51.2 + 6.4 * val) ms */
+#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS        0x04
+
+#define RT1715_REG_DRP_DUTY_CTRL                0xA3
+#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT      400
 
-#define RT1715_REG_VENDOR_5 0x9B
-#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF BIT(5)
-#define RT1715_REG_VENDOR_5_ENEXTMSG BIT(4)
+#define RT1715_REG_BMCIO_RXDZEN                 0xAF
+#define RT1715_REG_BMCIO_RXDZEN_ENABLE          0x01
+#define RT1715_REG_BMCIO_RXDZEN_DISABLE         0x00
 
-#define RT1715_REG_VENDOR_7 0xA0
-#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0)
+extern const struct tcpm_drv rt1715_tcpm_drv;
 
 #endif /* defined(__CROS_EC_USB_PD_TCPM_RT1715_H) */