diff options
| author | Bill Richardson <wfrichar@chromium.org> | 2013-08-09 10:59:35 -0700 |
|---|---|---|
| committer | Dave Parker <dparker@chromium.org> | 2013-08-09 23:39:28 -0700 |
| commit | 941245269b45cda57831e144caf62ba1fe1c310d (patch) | |
| tree | 7abd1166bf3dadf2d49e871da6ab823c537edcd5 | |
| parent | 23e85746b1f6ca38f590f6680159eae86f170fb7 (diff) | |
| download | chrome-ec-941245269b45cda57831e144caf62ba1fe1c310d.tar.gz | |
CHERRY-PICK:Haswell: shutdown directly to G3 without pausing in S5
We've been pausing in S5 for ten seconds for various arcane reasons related
to clock rates and USB peripherals. We don't need to do that anymore, and
there are other arcane reasons why it's better if we don't.
BUG=chrome-os-partner:21791
BRANCH=falco,peppy
TEST=manual
On the EC console, limit the output to just the chipset channel:
> chan 4
Now boot the AP, then shut down.
Before you'd see a ten-second pause in S5, like this:
[29.586858 x86 power state 3 = S0, in 0x00df]
[29.587268 x86 power state 7 = S0->S3, in 0x009f]
[29.587707 x86 power state 2 = S3, in 0x009f]
[29.587959 x86 power state 8 = S3->S5, in 0x009f]
[29.588474 x86 power state 1 = S5, in 0x009c]
[29.588733 x86 power state 1 = S5, in 0x009c]
[29.603317 x86 power state 1 = S5, in 0x0094]
[39.603612 x86 power state 9 = S5->G3, in 0x0094]
[39.604137 x86 power state 0 = G3, in 0x0000]
[39.604376 x86 power state 0 = G3, in 0x0000]
With this change the pause is gone:
[26.764160 x86 power state 3 = S0, in 0x00df]
[26.764570 x86 power state 7 = S0->S3, in 0x009f]
[26.765011 x86 power state 2 = S3, in 0x009f]
[26.765262 x86 power state 8 = S3->S5, in 0x009f]
[26.765777 x86 power state 9 = S5->G3, in 0x009c]
[26.766220 x86 power state 0 = G3, in 0x0008]
[26.766526 x86 power state 0 = G3, in 0x0008]
[26.770517 x86 power state 0 = G3, in 0x0000]
Change-Id: Ie60419309bd83b65f94fffb9a0835aefef953fc8
Original-Change-Id: I05e19ddfe9dfa1bcc2a29103d120910c4371b88e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65336
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65455
Commit-Queue: Dave Parker <dparker@chromium.org>
Reviewed-by: Dave Parker <dparker@chromium.org>
Tested-by: Dave Parker <dparker@chromium.org>
| -rw-r--r-- | common/chipset_haswell.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/common/chipset_haswell.c b/common/chipset_haswell.c index c5e5dec78c..f4417ce2a1 100644 --- a/common/chipset_haswell.c +++ b/common/chipset_haswell.c @@ -150,7 +150,6 @@ enum x86_state x86_handle_state(enum x86_state state) case X86_S5: if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) return X86_S5S3; /* Power up to next state */ - break; case X86_S3: @@ -217,14 +216,14 @@ enum x86_state x86_handle_state(enum x86_state state) /* Wait for the always-on rails to be good */ if (x86_wait_signals(IN_PGOOD_ALWAYS_ON)) { chipset_force_shutdown(); - return X86_S5; + return X86_S5G3; } /* Turn on power to RAM */ gpio_set_level(GPIO_PP1350_EN, 1); if (x86_wait_signals(IN_PGOOD_S3)) { chipset_force_shutdown(); - return X86_S5; + return X86_S5G3; } /* @@ -316,7 +315,7 @@ enum x86_state x86_handle_state(enum x86_state state) /* Disable PP5000 (5V) rail. */ gpio_set_level(GPIO_PP5000_EN, 0); - return X86_S5; + return X86_S5G3; case X86_S5G3: /* Deassert DPWROK, assert RSMRST# */ |