diff options
| author | Matt Wang <matt_wang@compal.corp-partner.google.com> | 2022-11-08 10:14:48 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-11-10 02:44:21 +0000 |
| commit | 8858f7d24a5023a1408d6194a6eec26b18d5c34a (patch) | |
| tree | 4113c059b6701224c18047cfa1caa52fbea5b285 | |
| parent | 9d1b3e82cb2af8201ccadec3b63fb279a85edff7 (diff) | |
| download | chrome-ec-8858f7d24a5023a1408d6194a6eec26b18d5c34a.tar.gz | |
winterhold: Adjust tuning for C1
C1 requires a different setting for the equalization and flat gain
register.
BUG=b:254616597
BRANCH=none
TEST=zmake build winterhold successfully
LOW_COVERAGE_REASON=no unit test for skyrim board yet: b/247151116
Signed-off-by: Matt Wang <matt_wang@compal.corp-partner.google.com>
Change-Id: Ibd0e8cdf769ff0f6404cc297b616221f14f8e445
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4011741
Reviewed-by: Diana Z <dzigterman@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com>
| -rw-r--r-- | zephyr/program/skyrim/src/winterhold/usb_mux_config.c | 83 |
1 files changed, 61 insertions, 22 deletions
diff --git a/zephyr/program/skyrim/src/winterhold/usb_mux_config.c b/zephyr/program/skyrim/src/winterhold/usb_mux_config.c index fdcf37e6b0..1eff945ed7 100644 --- a/zephyr/program/skyrim/src/winterhold/usb_mux_config.c +++ b/zephyr/program/skyrim/src/winterhold/usb_mux_config.c @@ -56,6 +56,20 @@ int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state) return anx7483_set_default_tuning(me, mux_state); } +int board_anx7483_c1_fg_defalut_tuning(const struct usb_mux *me) +{ + RETURN_ERROR( + anx7483_set_fg(me, ANX7483_PIN_URX1, ANX7483_FG_SETTING_1_2DB)); + RETURN_ERROR( + anx7483_set_fg(me, ANX7483_PIN_URX2, ANX7483_FG_SETTING_1_2DB)); + RETURN_ERROR( + anx7483_set_fg(me, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_1_2DB)); + RETURN_ERROR( + anx7483_set_fg(me, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_1_2DB)); + + return EC_SUCCESS; +} + int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; @@ -68,40 +82,65 @@ int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state) RETURN_ERROR(anx7483_set_default_tuning(me, mux_state)); + /* + * Set the Flat Gain to default every time, to prevent DP only mode's + * Flat Gain change in the last plug. + */ + RETURN_ERROR(board_anx7483_c1_fg_defalut_tuning(me)); + if (mux_state == USB_PD_MUX_USB_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, ANX7483_EQ_SETTING_12_5DB)); RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, ANX7483_EQ_SETTING_12_5DB)); + } else if (mux_state == USB_PD_MUX_DP_ENABLED) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1, + ANX7483_FG_SETTING_0_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2, + ANX7483_FG_SETTING_0_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1, + ANX7483_FG_SETTING_0_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2, + ANX7483_FG_SETTING_0_5DB)); } else if (mux_state == USB_PD_MUX_DOCK && !flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_8_4DB)); RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1, ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX2, + ANX7483_FG_SETTING_0_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX2, + ANX7483_FG_SETTING_0_5DB)); } else if (mux_state == USB_PD_MUX_DOCK && flipped) { + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1, + ANX7483_EQ_SETTING_8_4DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2, + ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1, + ANX7483_EQ_SETTING_8_4DB)); RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2, ANX7483_EQ_SETTING_12_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_URX1, + ANX7483_FG_SETTING_0_5DB)); + RETURN_ERROR(anx7483_set_fg(me, ANX7483_PIN_UTX1, + ANX7483_FG_SETTING_0_5DB)); } - /* - * Those registers all need to be set no matter what state the mux is - * in it needs to be set. - */ - RETURN_ERROR( - anx7483_set_eq(me, ANX7483_PIN_URX1, ANX7483_EQ_SETTING_8_4DB)); - RETURN_ERROR( - anx7483_set_eq(me, ANX7483_PIN_URX2, ANX7483_EQ_SETTING_8_4DB)); - RETURN_ERROR( - anx7483_set_eq(me, ANX7483_PIN_UTX1, ANX7483_EQ_SETTING_8_4DB)); - RETURN_ERROR( - anx7483_set_eq(me, ANX7483_PIN_UTX2, ANX7483_EQ_SETTING_8_4DB)); - - RETURN_ERROR( - anx7483_set_fg(me, ANX7483_PIN_URX1, ANX7483_FG_SETTING_0_5DB)); - RETURN_ERROR( - anx7483_set_fg(me, ANX7483_PIN_URX2, ANX7483_FG_SETTING_0_5DB)); - RETURN_ERROR( - anx7483_set_fg(me, ANX7483_PIN_UTX1, ANX7483_FG_SETTING_0_5DB)); - RETURN_ERROR( - anx7483_set_fg(me, ANX7483_PIN_UTX2, ANX7483_FG_SETTING_0_5DB)); - return EC_SUCCESS; } |