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authorRandall Spangler <rspangler@chromium.org>2012-03-12 18:25:37 -0700
committerRandall Spangler <rspangler@chromium.org>2012-03-12 18:25:37 -0700
commitdcb1d1f9299fb6d78814a072114c2eab0f7d3198 (patch)
tree0a08f91fcfabdae23e069b00ad0a5ebb032af206
parent186deea4c4388d0d019ae12b849ae1341dffe9fc (diff)
downloadchrome-ec-dcb1d1f9299fb6d78814a072114c2eab0f7d3198.tar.gz
Add x86 reset support
(new method, and x86reset command to call it) Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8460 TEST=manual: powerbtn, wait for system to boot, x86reset Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
-rw-r--r--common/x86_power.c22
-rw-r--r--include/x86_power.h3
2 files changed, 25 insertions, 0 deletions
diff --git a/common/x86_power.c b/common/x86_power.c
index 4435142fcd..8a9664932c 100644
--- a/common/x86_power.c
+++ b/common/x86_power.c
@@ -173,6 +173,19 @@ void x86_power_force_shutdown(void)
/* TODO: crosbug.com/p/8242 - real implementation */
}
+
+void x86_power_reset(void)
+{
+ /* Ignore if RCINn is already low */
+ if (gpio_get_level(GPIO_PCH_RCINn) == 0)
+ return;
+
+ /* Pulse must be at least 16 PCI clocks long = 500ns */
+ gpio_set_level(GPIO_PCH_RCINn, 0);
+ udelay(10);
+ gpio_set_level(GPIO_PCH_RCINn, 1);
+}
+
/*****************************************************************************/
/* Chipset interface */
@@ -414,3 +427,12 @@ static int command_x86power(int argc, char **argv)
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(x86power, command_x86power);
+
+
+static int command_x86reset(int argc, char **argv)
+{
+ /* Force the x86 to reset */
+ x86_power_reset();
+ return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(x86reset, command_x86reset);
diff --git a/include/x86_power.h b/include/x86_power.h
index 41191b4d3f..a093798c50 100644
--- a/include/x86_power.h
+++ b/include/x86_power.h
@@ -25,4 +25,7 @@ void x86_power_cpu_overheated(int too_hot);
* intended for use when the system is too hot or battery power is critical. */
void x86_power_force_shutdown(void);
+/* Pulse the reset line to the x86. */
+void x86_power_reset(void);
+
#endif /* __CROS_EC_X86_POWER_H */