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authorAlec Berg <alecaberg@chromium.org>2014-09-19 13:48:56 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-09-24 23:28:07 +0000
commit5e7c09ed3eafd548723b58fe108ef5a777158a8d (patch)
treed626b0306743017100ab1aa8990c25460e0f8739
parent9bebf41d169d3cac003972a78c4ba46fdd60687c (diff)
downloadchrome-ec-5e7c09ed3eafd548723b58fe108ef5a777158a8d.tar.gz
stm32f0: samus_pd: add hibernate and enable wake pins for samus
Add hibernate functionality for stm32f0, and enable wake pins for samus PD MCU. Samus wake pins are VBUS present on either port. BUG=chrome-os-partner:31226 BRANCH=none TEST=load onto samus PD. test hibernate console command: > hibernate 0 500000 Hibernating for 0.500000 s (5 seconds later) --- UART initialized after reboot --- [Reset cause: hibernate] ... > hibernate Hibernating until wake pin asserted. (plug in AC) --- UART initialized after reboot --- [Reset cause: hibernate] Change-Id: Ib86f2677721df29e7bf6975e239de79c25a38795 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219105 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r--board/samus_pd/board.h1
-rw-r--r--chip/stm32/clock-stm32f.c2
-rw-r--r--chip/stm32/clock-stm32f0.c24
-rw-r--r--chip/stm32/registers.h12
-rw-r--r--include/config.h3
5 files changed, 41 insertions, 1 deletions
diff --git a/board/samus_pd/board.h b/board/samus_pd/board.h
index a3364071b7..7f9bddc838 100644
--- a/board/samus_pd/board.h
+++ b/board/samus_pd/board.h
@@ -19,6 +19,7 @@
#define CONFIG_ADC
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_FORCE_CONSOLE_RESUME
+#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP3|STM32_PWR_CSR_EWUP8)
#define CONFIG_HW_CRC
#define CONFIG_I2C
#undef CONFIG_LID_SWITCH
diff --git a/chip/stm32/clock-stm32f.c b/chip/stm32/clock-stm32f.c
index 0cac173965..301b4c09ef 100644
--- a/chip/stm32/clock-stm32f.c
+++ b/chip/stm32/clock-stm32f.c
@@ -170,7 +170,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
asm volatile("cpsid i");
/* enable the wake up pin */
- STM32_PWR_CSR |= (1<<8);
+ STM32_PWR_CSR |= STM32_PWR_CSR_EWUP;
STM32_PWR_CR |= 0xe;
CPU_SCB_SYSCTRL |= 0x4;
/* go to Standby mode */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index 99ef0b2681..bcb72fa070 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -258,6 +258,30 @@ static void config_hispeed_clock(void)
#endif
}
+void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+ uint32_t rtc, rtcss;
+
+ if (seconds || microseconds)
+ set_rtc_alarm(seconds, microseconds, &rtc, &rtcss);
+
+ /* interrupts off now */
+ asm volatile("cpsid i");
+
+#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
+ /* enable the wake up pins */
+ STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
+#endif
+ STM32_PWR_CR |= 0xe;
+ CPU_SCB_SYSCTRL |= 0x4;
+ /* go to Standby mode */
+ asm("wfi");
+
+ /* we should never reach that point */
+ while (1)
+ ;
+}
+
#ifdef CONFIG_LOW_POWER_IDLE
void clock_refresh_console_in_use(void)
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 351b1a657d..9922aaad11 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -493,6 +493,18 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
#define STM32_PWR_CR_LPSDSR (1 << 0)
#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+#if defined(CHIP_FAMILY_STM32F)
+#define STM32_PWR_CSR_EWUP (1 << 8)
+#elif defined(CHIP_FAMILY_STM32F0)
+#define STM32_PWR_CSR_EWUP1 (1 << 8)
+#define STM32_PWR_CSR_EWUP2 (1 << 9)
+#define STM32_PWR_CSR_EWUP3 (1 << 10)
+#define STM32_PWR_CSR_EWUP4 (1 << 11)
+#define STM32_PWR_CSR_EWUP5 (1 << 12)
+#define STM32_PWR_CSR_EWUP6 (1 << 13)
+#define STM32_PWR_CSR_EWUP7 (1 << 14)
+#define STM32_PWR_CSR_EWUP8 (1 << 15)
+#endif
#if defined(CHIP_FAMILY_STM32L)
#define STM32_RCC_BASE 0x40023800
diff --git a/include/config.h b/include/config.h
index 3f6598b50e..bf2c76618d 100644
--- a/include/config.h
+++ b/include/config.h
@@ -570,6 +570,9 @@
/* Enable system hibernate */
#define CONFIG_HIBERNATE
+/* For ECs with multiple wakeup pins, define enabled wakeup pins */
+#undef CONFIG_HIBERNATE_WAKEUP_PINS
+
/*****************************************************************************/
/* I2C configuration */