honeybuns: Initial /board files

Modified version of /board/fruitpie.
Attempted to capture GPIO definitions. Other changes
consisted of modifying functions to enable compilation.
No real functionality as of yet.

TEST=Serial console and I2C functions have been verified
BUG=chrome-os-partner:37078
BRANCH=samus

Change-Id: Iedfc724a058e4220176193ef0f66e5bf45eabbd9
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/252426
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

8 files changed, 728 insertions, 0 deletions

diff --git a/board/honeybuns/board.c b/board/honeybuns/board.c
new file mode 100644
index 0000000000..491c736cfc
--- /dev/null
+++ b/board/honeybuns/board.c
@@ -0,0 +1,131 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Honeybuns board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "usb.h"
+#include "usb_pd.h"
+#include "util.h"
+
+
+
+void vbus_event(enum gpio_signal signal)
+{
+	ccprintf("VBUS!\n");
+}
+
+
+#include "gpio_list.h"
+
+
+static void honeybuns_test_led_update(void)
+{
+	static int toggle_count;
+	toggle_count++;
+
+	gpio_set_level(GPIO_TP6, toggle_count&1);
+}
+DECLARE_HOOK(HOOK_TICK, honeybuns_test_led_update, HOOK_PRIO_DEFAULT);
+
+/* Initialize board. */
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= 1 << 0;
+
+	/*
+	 * the DMA mapping is :
+	 *  Chan 2 : TIM1_CH1  (C0 RX)
+	 *  Chan 3 : SPI1_TX   (C0 TX)
+	 *  Chan 4 : USART1_TX
+	 *  Chan 5 : USART1_RX
+	 *  Chan 6 :
+	 *  Chan 7 :
+	 */
+	/* Remap USART DMA to match the USART driver */
+	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);
+}
+
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
+	/* VBUS sense via 100k/8.8k voltage divder 3.3V -> 40.8V */
+	[ADC_CH_VIN_DIV_P] = {"VIN_DIV_P", 40800, 4096, 0, STM32_AIN(5)},
+	[ADC_CH_VIN_DIV_N] = {"VIN_DIV_N", 40800, 4096, 0, STM32_AIN(6)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"master", I2C_PORT_MASTER, 100,
+		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const void * const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Honeybuns"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+
+
+
+void board_set_usb_mux(int port, enum typec_mux mux, int polarity)
+{
+
+	if (mux == TYPEC_MUX_NONE) {
+		/* put the mux in the high impedance state */
+		gpio_set_level(GPIO_SS_MUX_OE_L, 1);
+		return;
+	}
+
+	if ((mux == TYPEC_MUX_DOCK) || (mux == TYPEC_MUX_USB)) {
+		/* Low selects USB Dock */
+		gpio_set_level(GPIO_SS_MUX_SEL, 0);
+	} else if (mux == TYPEC_MUX_DP) {
+		/* high selects display port */
+		gpio_set_level(GPIO_SS_MUX_SEL, 1);
+	}
+
+	/* clear OE line to make mux active */
+	gpio_set_level(GPIO_SS_MUX_OE_L, 0);
+}
+
+int board_get_usb_mux(int port, const char **dp_str, const char **usb_str)
+{
+	int oe_disabled = gpio_get_level(GPIO_SS_MUX_OE_L);
+	int dp_4lanes = gpio_get_level(GPIO_SS_MUX_SEL);
+
+	if (oe_disabled) {
+		*usb_str = NULL;
+		*dp_str = NULL;
+		return 0;
+	}
+
+	if (dp_4lanes) {
+		*dp_str = "DP_4LANE";
+		*usb_str = NULL;
+	} else {
+		*dp_str = "DP_2LANE";
+		*usb_str = "DOCK";
+	}
+	return 1;
+}
diff --git a/board/honeybuns/board.h b/board/honeybuns/board.h
new file mode 100644
index 0000000000..781467144b
--- /dev/null
+++ b/board/honeybuns/board.h
@@ -0,0 +1,89 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Honeybuns board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#define CONFIG_UART_CONSOLE 1
+
+/* Optional features */
+#define CONFIG_ADC
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#undef CONFIG_LID_SWITCH
+#define CONFIG_STM_HWTIMER32
+#undef CONFIG_TASK_PROFILING
+#define CONFIG_USB
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#undef CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_CUSTOM_VDM
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_INTERNAL_COMP
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#undef CONFIG_WATCHDOG_HELP
+
+
+
+/* I2C ports configuration */
+#define I2C_PORT_MASTER 0
+
+/* USB configuration */
+#define CONFIG_USB_PID 0x5015
+/* By default, enable all console messages excepted USB */
+#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_USB))
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+#include "gpio_signal.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_CH_CC1_PD = 0,
+	ADC_CH_VIN_DIV_P,
+	ADC_CH_VIN_DIV_N,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_VERSION,
+	USB_STR_BB_URL,
+
+	USB_STR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+/* USB interface indexes (use define rather than enum to expand them) */
+#define USB_IFACE_COUNT        0
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL		0
+#define USB_EP_COUNT		1
+
+#endif /* __BOARD_H */
diff --git a/board/honeybuns/build.mk b/board/honeybuns/build.mk
new file mode 100644
index 0000000000..7058e7ca57
--- /dev/null
+++ b/board/honeybuns/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072CBU6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/honeybuns/ec.tasklist b/board/honeybuns/ec.tasklist
new file mode 100644
index 0000000000..72649e8217
--- /dev/null
+++ b/board/honeybuns/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)
diff --git a/board/honeybuns/gpio.inc b/board/honeybuns/gpio.inc
new file mode 100644
index 0000000000..e61972a6a3
--- /dev/null
+++ b/board/honeybuns/gpio.inc
@@ -0,0 +1,55 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*GPIO(DP_HPD,            A, 0,  GPIO_INT_BOTH, hpd_event)*/
+GPIO(DP_HPD,            A, 0,  GPIO_INPUT, NULL)
+
+/* PD RX/TX */
+GPIO(USB_CC1_PD,        A, 1,  GPIO_ANALOG,  NULL)
+GPIO(PD_VBUS_P,         A, 5,  GPIO_ANALOG,  NULL)
+GPIO(PD_VBUS_N,         A, 6,  GPIO_ANALOG,  NULL)
+GPIO(PD_TX_EN,          A, 15, GPIO_OUT_LOW, NULL)
+GPIO(PD_TX_DATA,        B, 4,  GPIO_OUT_LOW, NULL)
+
+/* Power and muxes control */
+GPIO(PP20000_EN,        A, 8,  GPIO_OUT_LOW,  NULL)
+GPIO(PPVAR_VBUS_EN,     B, 12, GPIO_OUT_LOW,  NULL)
+GPIO(SS_MUX_OE_L,       B, 13, GPIO_OUT_HIGH, NULL)
+GPIO(SS_MUX_SEL,        B, 14, GPIO_OUT_LOW,  NULL)
+
+/* Display Port/HDMI */
+GPIO(PD_SBU_ENABLE,     A, 7,  GPIO_OUT_LOW, NULL)
+
+/* Chip Resets */
+GPIO(BRIDGE_RESET_L,    B, 0,  GPIO_OUT_HIGH, NULL)
+GPIO(SPLITTER_RESET_L,  B, 1,  GPIO_OUT_HIGH, NULL)
+GPIO(HUB_RESET_L,       B, 15, GPIO_OUT_HIGH, NULL)
+
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(MASTER_I2C_SCL,    B, 6,  GPIO_INPUT, NULL)
+GPIO(MASTER_I2C_SDA,    B, 7,  GPIO_INPUT, NULL)
+
+
+/* Test points */
+GPIO(TP6,               A, 13, GPIO_OUT_HIGH /*GPIO_ODR_HIGH*/, NULL)
+GPIO(TP7,               A, 14, GPIO_OUT_LOW /*GPIO_ODR_HIGH*/, NULL)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+ALTERNATE(B, 0x0018, 0, MODULE_USB_PD, 0)            /* SPI1 SCK/MISO: PB3/PB4 */
+ALTERNATE(B, 0x0200, 2, MODULE_USB_PD, 0)            /* TIM17_CH1: PB9 */
+ALTERNATE(A, 0x0600, 1, MODULE_UART,   GPIO_PULL_UP) /* USART1: PA9/PA10 */
+ALTERNATE(A, 0x000C, 1, MODULE_UART,   GPIO_PULL_UP) /* USART2: PA2/PA3 */
+ALTERNATE(B, 0x0C00, 4, MODULE_UART,   GPIO_PULL_UP) /* USART3: PB10/PB11 */
+ALTERNATE(B, 0x00C0, 1, MODULE_I2C,    0)            /* I2C MASTER: PB6/PB7 */
+
diff --git a/board/honeybuns/usb_pd_config.h b/board/honeybuns/usb_pd_config.h
new file mode 100644
index 0000000000..e4e16dc5cd
--- /dev/null
+++ b/board/honeybuns/usb_pd_config.h
@@ -0,0 +1,173 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery board configuration */
+
+#ifndef __USB_PD_CONFIG_H
+#define __USB_PD_CONFIG_H
+
+/* Port and task configuration */
+#define PD_PORT_COUNT 1
+#define PORT_TO_TASK_ID(port) TASK_ID_PD
+#define TASK_ID_TO_PORT(id)   0
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX_C0 17
+#define TIM_CLOCK_PD_RX_C0 1
+
+#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
+#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
+
+/* Timer channel */
+#define TIM_RX_CCR_C0 1
+#define TIM_TX_CCR_C0 1
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_RX_CCR_REG(p) TIM_CCR_C0
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX(p) TIM_REG_TX_C0
+#define TIM_REG_RX(p) TIM_REG_RX_C0
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX is using SPI1 on PB4 */
+#define SPI_REGS(p) STM32_SPI1_REGS
+
+static inline void spi_enable_clock(int port)
+{
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+}
+
+/* SPI1_TX no remap needed */
+#define DMAC_SPI_TX(p) STM32_DMAC_CH3
+
+/* RX is using COMP1 triggering TIM1 CH1 */
+#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
+#define CMP2OUTSEL 0
+
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_CCR_CS  1
+#define EXTI_COMP_MASK(p) (1 << 21)
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+#define DMAC_TIM_RX(p) STM32_DMAC_CH2
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(int port)
+{
+	/* 40 Mhz pin speed on TX_EN (PA15) */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000;
+	/* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0;
+}
+
+/* Reset SPI peripheral used for TX */
+static inline void pd_tx_spi_reset(int port)
+{
+	/* Reset SPI1 */
+	STM32_RCC_APB1RSTR |= (1 << 12);
+	STM32_RCC_APB1RSTR &= ~(1 << 12);
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int port, int polarity)
+{
+	/* PB4 is SPI1_MISO */
+	gpio_set_alternate_function(GPIO_B, 0x0010, 0);
+
+	gpio_set_level(GPIO_PD_TX_EN, 1);
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int port, int polarity)
+{
+	/* TX_DATA on PB4 is an output low GPIO to disable the FET */
+	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4)))
+							     |  (1 << (2*4));
+	/*
+	 * Tri-state the low side after the high side
+	 * to ensure we are not going above Vnc
+	 */
+	gpio_set_level(GPIO_PD_TX_EN, 0);
+}
+
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int port, int polarity)
+{
+	/*
+	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
+	 * use VrefInt / 2 as INM (about 600mV)
+	 */
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
+		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+	gpio_config_module(MODULE_USB_PD, 1);
+}
+
+
+static inline void pd_set_host_mode(int port, int enable)
+{
+	if (!enable)
+		gpio_set_level(GPIO_PPVAR_VBUS_EN, 0);
+}
+
+static inline void pd_config_init(int port, uint8_t power_role)
+{
+	/* Initialize TX pins and put them in Hi-Z */
+	pd_tx_init();
+}
+
+static inline int pd_adc_read(int port, int cc)
+{
+	/* only one CC line, assume other one is always low */
+	return (cc == 0) ? adc_read_channel(ADC_CH_CC1_PD) : 0;
+}
+
+
+static inline void pd_set_vconn(int port, int polarity, int enable)
+{
+
+}
+
+static inline int pd_snk_is_vbus_provided(int port)
+{
+	return 0;
+}
+
+/* Standard-current DFP : no-connect voltage is 1.55V */
+#define PD_SRC_VNC 1550 /* mV */
+
+/* UFP-side : threshold for DFP connection detection */
+#define PD_SNK_VA   200 /* mV */
+
+/* we are acting only as a source */
+#define PD_DEFAULT_STATE PD_STATE_SRC_DISCONNECTED
+
+/* delay necessary for the voltage transition on the power supply */
+/* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078)
+ * Need to measure these and adjust for honeybuns.
+ */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
+
+/* Define typical operating power and max power */
+#define PD_OPERATING_POWER_MW 1000
+#define PD_MAX_POWER_MW       60000
+#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_VOLTAGE_MV     20000
+
+#endif /* __USB_PD_CONFIG_H */
diff --git a/board/honeybuns/usb_pd_policy.c b/board/honeybuns/usb_pd_policy.c
new file mode 100644
index 0000000000..7e45a0cc87
--- /dev/null
+++ b/board/honeybuns/usb_pd_policy.c
@@ -0,0 +1,243 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_pd.h"
+
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_EXTERNAL | PDO_FIXED_DUAL_ROLE | \
+			 PDO_FIXED_DATA_SWAP)
+
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
+		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/* Holds valid object position (opos) for entered mode */
+static int alt_mode[PD_AMODE_COUNT];
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+
+}
+
+
+int pd_is_valid_input_voltage(int mv)
+{
+	/* Any voltage less than the max is allowed */
+	return 1;
+}
+
+int pd_check_requested_voltage(uint32_t rdo)
+{
+	int max_ma = rdo & 0x3FF;
+	int op_ma = (rdo >> 10) & 0x3FF;
+	int idx = rdo >> 28;
+	uint32_t pdo;
+	uint32_t pdo_ma;
+
+	if (!idx || idx > pd_src_pdo_cnt)
+		return EC_ERROR_INVAL; /* Invalid index */
+
+	/* check current ... */
+	pdo = pd_src_pdo[idx - 1];
+	pdo_ma = (pdo & 0x3ff);
+	if (op_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much op current */
+	if (max_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much max current */
+
+	CPRINTF("Requested %d V %d mA (for %d/%d mA)\n",
+		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
+		 ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
+
+	return EC_SUCCESS;
+}
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* provide VBUS */
+	gpio_set_level(GPIO_PPVAR_VBUS_EN, 1);
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Kill VBUS */
+	gpio_set_level(GPIO_PPVAR_VBUS_EN, 0);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_power_swap(int port)
+{
+	/* Always allow power swap */
+	return 1;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Always allow data swap */
+	return 1;
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+	/* Do nothing */
+}
+
+void pd_check_pr_role(int port, int pr_role, int partner_pr_swap)
+{
+}
+
+void pd_check_dr_role(int port, int dr_role, int partner_dr_swap)
+{
+}
+
+int pd_alt_mode(int port, uint16_t svid)
+{
+	if (svid == USB_SID_DISPLAYPORT)
+		return alt_mode[PD_AMODE_DISPLAYPORT];
+	else if (svid == USB_VID_GOOGLE)
+		return alt_mode[PD_AMODE_GOOGLE];
+	return 0;
+}
+
+
+/* ----------------- Vendor Defined Messages ------------------ */
+/* TODO () The VDM section needs to be updated for honeybuns */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* if last word is present, it contains lots of info */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				VDO_INFO_IS_RW(payload[6]));
+		}
+		/* copy hash */
+		if (cnt >= 6)
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+
+		break;
+	}
+
+	return 0;
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		CPRINTF("Entering mode w/ vdo = %08x\n", mode_caps);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int dp_on;
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS);
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   dp_on,
+				   0, /* power low? ... no */
+				   dp_on);
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	board_set_usb_mux(port, TYPEC_MUX_DP, pd_get_polarity(port));
+	dp_on = 1;
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG);
+	payload[1] = VDO_DP_CFG(MODE_DP_PIN_E, /* sink pins */
+				MODE_DP_PIN_E, /* src pins */
+				1,             /* DPv1.3 signaling */
+				2);	       /* UFP connected */
+	return 2;
+};
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	return 1; /* ack */
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	CPRINTF("Exiting mode\n");
+	/* return to safe config */
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
diff --git a/util/flash_ec b/util/flash_ec
index d43e4a09c8..283056511d 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -64,6 +64,7 @@ BOARDS_STM32=(
 	discovery
 	firefly
 	fruitpie
+	honeybuns
 	jerry
 	kitty
 	llama