diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-22 12:41:08 -0500 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-22 12:29:11 -0700 |
| commit | 3ca68b3134ae53f707a464458060d45f0a8a9ce4 (patch) | |
| tree | e7877a66ba29a6e6b79747e48d838843bd176526 | |
| parent | 93ec62ebc3ae238749915f8161a2673a7d2928d9 (diff) | |
| download | chrome-ec-3ca68b3134ae53f707a464458060d45f0a8a9ce4.tar.gz | |
haswell: fix RCIN# GPIO setting
The gpio pin used for RCIN# should be configured as open drain as the
rail is pulled up by a non-EC rail. Driving it high would leak power.
The current GPIO_HI_Z macro uses GPIO_HIGH as the default state.
However, it has been found that this actually drives the pin to ground.
It is still unclear how Link works or doesn't.
BUG=chrome-os-partner:19355
BRANCH=none
TEST=manual: boot on slippy without RCIN# causing reset and
the 'apreset warm' EC command works as expected.
Change-Id: I71425075f8d77b3d7e576a59fc24f823790e2655
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56269
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
| -rw-r--r-- | board/slippy/board.c | 2 | ||||
| -rw-r--r-- | common/x86_power_haswell.c | 10 | ||||
| -rw-r--r-- | include/gpio.h | 1 |
3 files changed, 9 insertions, 4 deletions
diff --git a/board/slippy/board.c b/board/slippy/board.c index 5fe222ff33..55f1d4a8d8 100644 --- a/board/slippy/board.c +++ b/board/slippy/board.c @@ -95,7 +95,7 @@ const struct gpio_info gpio_list[GPIO_COUNT] = { {"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL}, {"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, - {"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_OUT_HIGH, NULL}, + {"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_HI_Z_OPEN, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL}, {"TOUCHSCREEN_RESET_L", LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL}, diff --git a/common/x86_power_haswell.c b/common/x86_power_haswell.c index ecc18624af..9185053174 100644 --- a/common/x86_power_haswell.c +++ b/common/x86_power_haswell.c @@ -237,10 +237,14 @@ void chipset_reset(int cold_reset) * PLTRST# to reset the rest of the system. */ - /* Pulse must be at least 16 PCI clocks long = 500 ns */ - gpio_set_level(GPIO_PCH_RCIN_L, 0); - udelay(10); + /* + * Pulse must be at least 16 PCI clocks long = 500 ns. The gpio + * pin used by the EC is configured as open drain. Therefore, + * the driving RCIN# low needs to the level 1 to enable the + * FET and 0 to disable the FET. */ gpio_set_level(GPIO_PCH_RCIN_L, 1); + udelay(10); + gpio_set_level(GPIO_PCH_RCIN_L, 0); } } diff --git a/include/gpio.h b/include/gpio.h index 793b54575d..20ab664864 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -29,6 +29,7 @@ #define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) #define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH) #define GPIO_HI_Z (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) +#define GPIO_HI_Z_OPEN (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) #define GPIO_INT_EDGE (GPIO_INT_RISING | GPIO_INT_FALLING | GPIO_INT_BOTH) #define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) #define GPIO_INT_ANY (GPIO_INT_EDGE | GPIO_INT_LEVEL) |