it8380dev: fix ec2i and uart

1. Host access to the PNPCFG registers is disabled.
2. UART2 for host if necessary.

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=1. host can't access the PNPCFG registers.
     2. out I/O port 0x2f8 '0x30, 0x31, 0x32, 0x33, and 0x34'
        will have console message '01234'.

Change-Id: If07bdc129105f5248661d929e6858d4063c452ee
Reviewed-on: https://chromium-review.googlesource.com/300266
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

6 files changed, 90 insertions, 6 deletions

diff --git a/board/it8380dev/board.c b/board/it8380dev/board.c
index bf0edee14d..1223e01c65 100644
--- a/board/it8380dev/board.c
+++ b/board/it8380dev/board.c
@@ -144,6 +144,29 @@ const struct ec2i_t pnpcfg_settings[] = {
 	{HOST_INDEX_DSLDC5, P80L_P80LE},
 	/* P80L Current Index */
 	{HOST_INDEX_DSLDC6, P80L_P80LC},
+#ifdef CONFIG_UART_HOST
+	/* Select logical device 2h(UART2) */
+	{HOST_INDEX_LDN, LDN_UART2},
+	/*
+	 * I/O port base address is 2F8h.
+	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
+	 * See specification 7.24.4 for more detial.
+	 */
+	{HOST_INDEX_IOBAD0_MSB, 0x02},
+	{HOST_INDEX_IOBAD0_LSB, 0xF8},
+	/* IRQ number is 3 */
+	{HOST_INDEX_IRQNUMX, 0x03},
+	/*
+	 * Interrupt Request Type Select
+	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
+	 *       1: IRQ request is inverted before being applied to SERIRQ.
+	 * bit0, 0: Edge triggered mode.
+	 *       1: Level triggered mode.
+	 */
+	{HOST_INDEX_IRQTP, 0x02},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(pnpcfg_settings) == EC2I_SETTING_COUNT);
 
diff --git a/board/it8380dev/board.h b/board/it8380dev/board.h
index b477ed9c3d..13db5ed5e9 100644
--- a/board/it8380dev/board.h
+++ b/board/it8380dev/board.h
@@ -21,6 +21,7 @@
 #define CONFIG_POWER_BUTTON
 /* Use CS0 of SSPI */
 #define CONFIG_SPI_FLASH_PORT 0
+#define CONFIG_UART_HOST
 
 /* Optional console commands */
 #define CONFIG_CMD_FLASH
@@ -94,6 +95,14 @@ enum ec2i_setting {
 	EC2I_SET_RTCT_P80LB,
 	EC2I_SET_RTCT_P80LE,
 	EC2I_SET_RTCT_P80LC,
+#ifdef CONFIG_UART_HOST
+	EC2I_SET_UART2_LDN,
+	EC2I_SET_UART2_IO_BASE_MSB,
+	EC2I_SET_UART2_IO_BASE_LSB,
+	EC2I_SET_UART2_IRQ,
+	EC2I_SET_UART2_IRQ_TYPE,
+	EC2I_SET_UART2_ENABLE,
+#endif
 	/* Number of EC2I settings */
 	EC2I_SETTING_COUNT
 };
diff --git a/board/it8380dev/gpio.inc b/board/it8380dev/gpio.inc
index 319ef54206..282fa6fe52 100644
--- a/board/it8380dev/gpio.inc
+++ b/board/it8380dev/gpio.inc
@@ -30,10 +30,18 @@ GPIO(I2C_C_SCL,      PIN(F, 6), GPIO_INPUT)
 #endif
 GPIO(I2C_C_SDA,      PIN(F, 7), GPIO_INPUT)
 
+#ifdef CONFIG_UART_HOST
+GPIO(UART2_SIN1,     PIN(H, 1), GPIO_INPUT)
+GPIO(UART2_SOUT1,    PIN(H, 2), GPIO_INPUT)
+#endif
+
 /* Unimplemented signals which we need to emulate for now */
 UNIMPLEMENTED(ENTERING_RW)
 
-ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART0 */
+ALTERNATE(PIN_MASK(B, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART1 */
+#ifdef CONFIG_UART_HOST
+ALTERNATE(PIN_MASK(H, 0x06), 1, MODULE_UART, 0)            /* UART2 */
+#endif
 ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_SPI, 0)             /* SSCK of SPI */
 ALTERNATE(PIN_MASK(C, 0x28), 3, MODULE_SPI, 0)             /* SMOSI/SMISO of SPI */
 ALTERNATE(PIN_MASK(G, 0x01), 3, MODULE_SPI, 0)             /* SSCE1# of SPI */
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index 210aad7d25..05266bec1b 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -59,8 +59,13 @@ static void ec2i_ec_access_disable(void)
 	/* Diable EC to I-Bus access. */
 	IT83XX_EC2I_IBCTL &= ~0x01;
 
+#ifdef CONFIG_IT83XX_PNPCFG_HOST_ACCESS
 	/* Enable host access */
 	IT83XX_EC2I_LSIOHA &= ~0x03;
+#else
+	/* Host access is disabled */
+	IT83XX_EC2I_LSIOHA &= ~0x02;
+#endif
 }
 
 /* EC2I write */
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
index 80227c34ae..550672804a 100644
--- a/chip/it83xx/uart.c
+++ b/chip/it83xx/uart.c
@@ -15,8 +15,9 @@
 #include "uart.h"
 #include "util.h"
 
-/* Traces on UART0 */
-#define UART_PORT 0
+/* Traces on UART1 */
+#define UART_PORT      0
+#define UART_PORT_HOST 1
 
 static int init_done;
 
@@ -151,21 +152,56 @@ static void uart_config(void)
 	IT83XX_UART_MCR(UART_PORT) = 0x08;
 }
 
+#ifdef CONFIG_UART_HOST
+static void host_uart_config(void)
+{
+	/*
+	 * Specify clock source of the UART is 24MHz,
+	 * must match CLK_UART_DIV_SEL.
+	 */
+	IT83XX_UART_CSSR(UART_PORT_HOST) = 0x01;
+	/* 8-N-1 and DLAB set to allow access to DLL and DLM registers. */
+	IT83XX_UART_LCR(UART_PORT_HOST) = 0x83;
+	/* Set divisor to set baud rate to 115200 */
+	IT83XX_UART_DLM(UART_PORT_HOST) = 0x00;
+	IT83XX_UART_DLL(UART_PORT_HOST) = 0x01;
+	/*
+	 * Clear DLAB bit to exclude access to DLL and DLM and give access to
+	 * RBR and THR.
+	 */
+	IT83XX_UART_LCR(UART_PORT_HOST) = 0x03;
+	/*
+	 * Enable TX and RX FIFOs and set RX FIFO interrupt level to the
+	 * minimum 1 byte.
+	 */
+	IT83XX_UART_FCR(UART_PORT_HOST) = 0x07;
+}
+#endif
+
 void uart_init(void)
 {
 	/* Waiting for when we can use the GPIO module to set pin muxing */
 	gpio_config_module(MODULE_UART, 1);
 
-	/* switch UART0 on without hardware flow control */
-	IT83XX_GPIO_GRC1 = 0x01;
+	/* switch UART1 on without hardware flow control */
+	IT83XX_GPIO_GRC1 |= 0x01;
 	IT83XX_GPIO_GRC6 |= 0x03;
 
 	/* Enable clocks to UART 1 and 2. */
 	clock_enable_peripheral(CGC_OFFSET_UART, 0, 0);
 
-	/* Config UART 0 only for now. */
+	/* Config UART 1 */
 	uart_config();
 
+#ifdef CONFIG_UART_HOST
+	/* bit2, reset UART2 */
+	IT83XX_GCTRL_RSTC4 |= (1 << 2);
+	/* SIN1/SOUT1 of UART 2 is enabled. */
+	IT83XX_GPIO_GRC1 |= (1 << 2);
+	/* Config UART 2 */
+	host_uart_config();
+#endif
+
 	/* clear interrupt status */
 	task_clear_pending_irq(IT83XX_IRQ_UART1);
 
diff --git a/include/config.h b/include/config.h
index 56bdbb0cd9..8cb9af0e79 100644
--- a/include/config.h
+++ b/include/config.h
@@ -1058,6 +1058,9 @@
 /* Interrupt for PECI module. (IT839X series and IT838X DX only) */
 #undef CONFIG_IT83XX_PECI_WITH_INTERRUPT
 
+/* Allow the host access to the PNPCFG registers */
+#undef CONFIG_IT83XX_PNPCFG_HOST_ACCESS
+
 /* To define it, if I2C channel C and PECI used at the same time. */
 #undef CONFIG_IT83XX_SMCLK2_ON_GPC7