diff options
author | Dino Li <dino.li@ite.com.tw> | 2015-10-28 21:52:04 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-01 19:45:57 -0800 |
commit | ba63ef190e5818e1221baaafd44fbc65aa10209b (patch) | |
tree | 214995440cf2d4ed23406154c21f8efe4fbba91c | |
parent | aa2db4401174e138fc0adcfcf9f5be3b1d778348 (diff) | |
download | chrome-ec-ba63ef190e5818e1221baaafd44fbc65aa10209b.tar.gz |
it8380dev: fix irq, jtag and system
[irq]
1. The chip_init_irqs() function clears all IERx and EXT_IERx registers.
[jtag]
2. Enable debug mode through SMBus.
[system]
3. remove console_force_enabled functions.
4. implement __no_hibernate, scratchpad and nvcontext functions.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:23575
TEST=1. IERx and EXT_IERx registers are all cleared after chip_init_irqs().
2. console command "scratchpad" and "hibernate".
3. bram bank0 index 0x10 ~ 0x1F (16 bytes) for
system_get_vbnvcontext() and system_set_vbnvcontext functions.
Change-Id: If044d50c69ae80b013ab646a3a6931cec7560ec4
Reviewed-on: https://chromium-review.googlesource.com/309390
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r-- | board/it8380dev/board.h | 1 | ||||
-rw-r--r-- | chip/it83xx/irq.c | 9 | ||||
-rw-r--r-- | chip/it83xx/jtag.c | 3 | ||||
-rw-r--r-- | chip/it83xx/registers.h | 17 | ||||
-rw-r--r-- | chip/it83xx/system.c | 80 |
5 files changed, 89 insertions, 21 deletions
diff --git a/board/it8380dev/board.h b/board/it8380dev/board.h index bb9d1dfad2..3a34ad2792 100644 --- a/board/it8380dev/board.h +++ b/board/it8380dev/board.h @@ -28,6 +28,7 @@ /* Optional console commands */ #define CONFIG_CMD_FLASH +#define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_STACKOVERFLOW /* Debug */ diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index f980147df4..93752f0c7c 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -8,6 +8,7 @@ #include "common.h" #include "irq_chip.h" #include "registers.h" +#include "util.h" #define IRQ_GROUP(n, cpu_ints...) \ {(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \ @@ -85,5 +86,11 @@ int chip_trigger_irq(int irq) void chip_init_irqs(void) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ + int i; + + /* Clear all IERx and EXT_IERx */ + for (i = 0; i < ARRAY_SIZE(irq_groups); i++) { + IT83XX_INTC_REG(irq_groups[i].ier_off) = 0; + IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(i)) = 0; + } } diff --git a/chip/it83xx/jtag.c b/chip/it83xx/jtag.c index b876d7f914..1943e0a031 100644 --- a/chip/it83xx/jtag.c +++ b/chip/it83xx/jtag.c @@ -11,5 +11,6 @@ void jtag_pre_init(void) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ + /* bit4, enable debug mode through SMBus */ + IT83XX_SMB_SLVISELR &= ~(1 << 4); } diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index df1339b241..c6fa88609c 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -940,6 +940,7 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) #define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE+0x05) #define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE+0x06) #define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE+0x07) +#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE+0x08) #define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE+0x09+ch) #define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE+0x40+(ch << 6)) #define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE+0x41+(ch << 6)) @@ -966,6 +967,17 @@ enum bram_indices { BRAM_IDX_RESET_FLAGS3 = 3, BRAM_IDX_LPC_ACCESS = 4, + /* index 5 ~ 7 are reserved */ + + BRAM_IDX_SCRATCHPAD = 8, + BRAM_IDX_SCRATCHPAD1 = 9, + BRAM_IDX_SCRATCHPAD2 = 0xa, + BRAM_IDX_SCRATCHPAD3 = 0xb, + /* index 0xc ~ 0xf are reserved */ + + /* NVCONTEXT uses 16 bytes */ + BRAM_IDX_NVCONTEXT = 0x10, + BRAM_IDX_NVCONTEXT_END = 0x1F, }; #define BRAM_RESET_FLAGS IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS) #define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1) @@ -975,6 +987,11 @@ enum bram_indices { #define BRAM_LPC_ACCESS IT83XX_BRAM_BANK0(BRAM_IDX_LPC_ACCESS) #define LPC_ACCESS_INT_BUSY 0x33 +#define BRAM_SCRATCHPAD IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD) +#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1) +#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2) +#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3) + #define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i) /* --- MISC (not implemented yet) --- */ diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 052aa3a1ff..6019c5f41b 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -16,9 +16,36 @@ #include "version.h" #include "watchdog.h" +void __no_hibernate(uint32_t seconds, uint32_t microseconds) +{ +#ifdef CONFIG_COMMON_RUNTIME + /* + * Hibernate not implemented on this platform. + * + * Until then, treat this as a request to hard-reboot. + */ + cprints(CC_SYSTEM, "hibernate not supported, so rebooting"); + cflush(); + system_reset(SYSTEM_RESET_HARD); +#endif +} + +void __enter_hibernate(uint32_t seconds, uint32_t microseconds) + __attribute__((weak, alias("__no_hibernate"))); + void system_hibernate(uint32_t seconds, uint32_t microseconds) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ +#ifdef CONFIG_HOSTCMD_PD + /* Inform the PD MCU that we are going to hibernate. */ + host_command_pd_request_hibernate(); + /* Wait to ensure exchange with PD before hibernating. */ + msleep(100); +#endif + + /* Flush console before hibernating */ + cflush(); + /* chip specific standby mode */ + __enter_hibernate(seconds, microseconds); } static void check_reset_cause(void) @@ -86,7 +113,7 @@ int system_is_reboot_warm(void) void system_pre_init(void) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ + /* No initialization required */ } @@ -117,6 +144,13 @@ void system_reset(int flags) BRAM_RESET_FLAGS3 = save_flags & 0xff; /* + * bit4, disable debug mode through SMBus. + * If we are in debug mode, we need disable it before triggering + * a soft reset or reset will fail. + */ + IT83XX_SMB_SLVISELR |= (1 << 4); + + /* * Writing invalid key to watchdog module triggers a soft reset. For * now this is the only option, no hard reset. */ @@ -130,14 +164,24 @@ void system_reset(int flags) int system_set_scratchpad(uint32_t value) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ - return 0; + BRAM_SCRATCHPAD3 = (value >> 24) & 0xff; + BRAM_SCRATCHPAD2 = (value >> 16) & 0xff; + BRAM_SCRATCHPAD1 = (value >> 8) & 0xff; + BRAM_SCRATCHPAD = value & 0xff; + + return EC_SUCCESS; } uint32_t system_get_scratchpad(void) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ - return 0; + uint32_t value = 0; + + value |= BRAM_SCRATCHPAD3 << 24; + value |= BRAM_SCRATCHPAD2 << 16; + value |= BRAM_SCRATCHPAD1 << 8; + value |= BRAM_SCRATCHPAD; + + return value; } static uint16_t system_get_chip_id(void) @@ -191,27 +235,25 @@ const char *system_get_chip_revision(void) int system_get_vbnvcontext(uint8_t *block) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ + int i; + + for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) + block[i] = IT83XX_BRAM_BANK0((BRAM_IDX_NVCONTEXT + i)); + return EC_SUCCESS; } int system_set_vbnvcontext(const uint8_t *block) { - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ - return EC_SUCCESS; -} + int i; -int system_set_console_force_enabled(int val) -{ - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ - return 0; -} + for (i = 0; i < EC_VBNV_BLOCK_SIZE; i++) + IT83XX_BRAM_BANK0((BRAM_IDX_NVCONTEXT + i)) = block[i]; -int system_get_console_force_enabled(void) -{ - /* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */ - return 0; + return EC_SUCCESS; } +#define BRAM_NVCONTEXT_SIZE (BRAM_IDX_NVCONTEXT_END - BRAM_IDX_NVCONTEXT + 1) +BUILD_ASSERT(EC_VBNV_BLOCK_SIZE <= BRAM_NVCONTEXT_SIZE); uintptr_t system_get_fw_reset_vector(uintptr_t base) { |