diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-03-27 19:28:47 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-28 21:55:19 -0700 |
| commit | c1acab5888d8ddd4e0eb0012ad3d59b2a1ba9c14 (patch) | |
| tree | b66898963571410ed1321e87e6833a357db4d864 | |
| parent | ef561a293f1641750bba635a9af4f380a9dfd32e (diff) | |
| download | chrome-ec-c1acab5888d8ddd4e0eb0012ad3d59b2a1ba9c14.tar.gz | |
npcx: pwm: Fix PWM module
- Fix incorrect use of pwm functions which take a channel number.
- Set power-down register according to PWMs that are actually enabled.
BUG=chrome-os-partner:51722
TEST=Run 'pwm 1 50` on kevin and verify that LED lights up.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If7bcc812b55d3b72f215cf41c264d34827db7e29
Reviewed-on: https://chromium-review.googlesource.com/335372
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
| -rw-r--r-- | chip/npcx/pwm.c | 10 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 3 |
2 files changed, 8 insertions, 5 deletions
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c index d89ff365c3..7d3a548382 100644 --- a/chip/npcx/pwm.c +++ b/chip/npcx/pwm.c @@ -101,6 +101,7 @@ void pwm_set_freq(enum pwm_channel ch, uint32_t freq, uint32_t res) void pwm_enable(enum pwm_channel ch, int enabled) { int mdl = pwm_channels[ch].channel; + /* Start or close PWM module */ UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_PWR, enabled); } @@ -189,7 +190,7 @@ void pwm_config(enum pwm_channel ch) int mdl = pwm_channels[ch].channel; /* Disable PWM for module configuration */ - pwm_enable(mdl, 0); + pwm_enable(ch, 0); /* Set PWM heartbeat mode is no heartbeat */ SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD, @@ -220,9 +221,12 @@ void pwm_config(enum pwm_channel ch) static void pwm_init(void) { int i; + uint8_t pd_mask = 0; - /* Enable the PWM module and delay a few clocks */ - clock_enable_peripheral(CGC_OFFSET_PWM, CGC_PWM_MASK, CGC_MODE_ALL); + /* Take enabled PWMs out of power-down state */ + for (i = 0; i < PWM_CH_COUNT; i++) + pd_mask |= (1 << pwm_channels[i].channel); + clock_enable_peripheral(CGC_OFFSET_PWM, pd_mask, CGC_MODE_ALL); for (i = 0; i < PWM_CH_COUNT; i++) pwm_config(i); diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3d5317f02c..011977d24e 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -774,12 +774,11 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_6 = 5, }; +/* TODO: set PD masks based upon actual peripheral usage */ #define CGC_KBS_MASK (1 << NPCX_PWDWN_CTL1_KBS_PD) #define CGC_UART_MASK (1 << NPCX_PWDWN_CTL1_UART_PD) #define CGC_FAN_MASK (1 << NPCX_PWDWN_CTL1_MFT1_PD) #define CGC_FIU_MASK (1 << NPCX_PWDWN_CTL1_FIU_PD) -#define CGC_PWM_MASK ((1 << NPCX_PWDWN_CTL2_PWM0_PD) | \ - (1 << NPCX_PWDWN_CTL2_PWM1_PD)) #define CGC_I2C_MASK ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \ (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \ (1 << NPCX_PWDWN_CTL3_SMB2_PD) | \ |