diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2016-06-23 11:30:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-23 17:44:25 -0700 |
| commit | 8c65294108db43a3717c5afa3017058c826f27b5 (patch) | |
| tree | af8a31d5143ee2f15c6d9c1ceeba112ea169c7d7 | |
| parent | 3d74ba28649814ced21d51f8455c47f4ce981476 (diff) | |
| download | chrome-ec-8c65294108db43a3717c5afa3017058c826f27b5.tar.gz | |
tpm: use proper locality zero SPI bus addresses
The "PC Client Protection Profile for TPM 2.0" document defines SPI
bus addresses for different localities. That definition is not honored
in the cr50 implementation, this patch fixes it: locality zero
register file is based off 0xd40000.
BRANCH=none
BUG=chrome-os-partner:54720
TEST=verified that upstream Linux driver is happy now
Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355610
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | common/tpm_registers.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/common/tpm_registers.c b/common/tpm_registers.c index 1462022fc3..0796b9b3c4 100644 --- a/common/tpm_registers.c +++ b/common/tpm_registers.c @@ -25,18 +25,19 @@ #define CPRINTS(format, args...) cprints(CC_TPM, format, ## args) #define CPRINTF(format, args...) cprintf(CC_TPM, format, ## args) +#define TPM_LOCALITY_0_SPI_BASE 0x00d40000 /* Register addresses for FIFO mode. */ -#define TPM_ACCESS 0 -#define TPM_INT_ENABLE 8 -#define TPM_INT_VECTOR 0xC -#define TPM_INT_STATUS 0x10 -#define TPM_INTF_CAPABILITY 0x14 -#define TPM_STS 0x18 -#define TPM_DATA_FIFO 0x24 -#define TPM_INTERFACE_ID 0x30 -#define TPM_DID_VID 0xf00 -#define TPM_RID 0xf04 +#define TPM_ACCESS (TPM_LOCALITY_0_SPI_BASE + 0) +#define TPM_INT_ENABLE (TPM_LOCALITY_0_SPI_BASE + 8) +#define TPM_INT_VECTOR (TPM_LOCALITY_0_SPI_BASE + 0xC) +#define TPM_INT_STATUS (TPM_LOCALITY_0_SPI_BASE + 0x10) +#define TPM_INTF_CAPABILITY (TPM_LOCALITY_0_SPI_BASE + 0x14) +#define TPM_STS (TPM_LOCALITY_0_SPI_BASE + 0x18) +#define TPM_DATA_FIFO (TPM_LOCALITY_0_SPI_BASE + 0x24) +#define TPM_INTERFACE_ID (TPM_LOCALITY_0_SPI_BASE + 0x30) +#define TPM_DID_VID (TPM_LOCALITY_0_SPI_BASE + 0xf00) +#define TPM_RID (TPM_LOCALITY_0_SPI_BASE + 0xf04) #define GOOGLE_VID 0x1ae0 #define GOOGLE_DID 0x0028 |