cr50: use the correct reset signal for gru and reef

Boards that have plt_rst_l had sys_rst_l currently use the two signals
to detect resets and reset the TPM. That meant that the TPM could reset
twice depending on the timing of those signals. On boards with
plt_rst_l, we should really just use that to detect system resets and
not sys_rst_l. On boards with plt_rst_l, sys_rst_l should only be used
as an output to trigger warm resets.

This change makes both boards use the gpio tpm_rst_l_in to detect AP
resets. That gpio will be connected to a different pin depending on
which board we are using. On Gru the gpio will be connected to diom0
which is sys_rst_l, and reef will use diom3 which is plt_rst_l.

BUG=chrome-os-partner:61789
BRANCH=none
TEST=manual
	Use cr50 servo to verify the contents of /var/cache survive
	reset after 'dut-control warm_reset:on sleep:0.5000
	warm_reset:off'

	test on gru and reef

	verify that the system can boot to kernel

	run 'sysrst pulse' and check that you only see one system reset

	use 'pinmux' to verify the pins for the two types of boards are
	setup properly

	on reef diom0 is an input, diom3 is an input with wake_falling,
	and gpio1_gpio1 uses diom3

	on gru check that diom0 is an input with wake_falling, diom3 is
	not configured, and gpio1_gpio1 uses diom0

Change-Id: I1f6e8bfa525ffa5585a18282b78014f36f0cfee6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428130
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 70 insertions, 42 deletions

diff --git a/board/cr50/board.c b/board/cr50/board.c
index 6e0726bdfe..fe23db81de 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -88,7 +88,7 @@ int board_has_ap_usb(void)
 	return !!(board_properties & BOARD_USB_AP);
 }
 
-int board_has_plt_rst(void)
+int board_use_plt_rst(void)
 {
 	return !!(board_properties & BOARD_USE_PLT_RESET);
 }
@@ -265,7 +265,7 @@ static void init_pmu(void)
 void pmu_wakeup_interrupt(void)
 {
 	int exiten, wakeup_src;
-	int plt_rst_asserted;
+	int wake_on_low;
 
 	delay_sleep_by(1 * MSEC);
 
@@ -295,14 +295,13 @@ void pmu_wakeup_interrupt(void)
 		/*
 		 * If sys_rst_l or plt_rst_l (if signal is present) is
 		 * configured to wake on low and the signal is low, then call
-		 * sys_rst_asserted
+		 * tpm_rst_asserted
 		 */
-		plt_rst_asserted = board_properties & BOARD_USE_PLT_RESET ?
-			!gpio_get_level(GPIO_PLT_RST_L) : 0;
-		if ((!gpio_get_level(GPIO_SYS_RST_L_IN) &&
-		     GREAD_FIELD(PINMUX, EXITINV0, DIOM0)) || (plt_rst_asserted
-		     && GREAD_FIELD(PINMUX, EXITINV0, DIOM3)))
-			sys_rst_asserted(GPIO_SYS_RST_L_IN);
+		wake_on_low = board_use_plt_rst() ?
+			GREAD_FIELD(PINMUX, EXITINV0, DIOM3) :
+			GREAD_FIELD(PINMUX, EXITINV0, DIOM0);
+		if (!gpio_get_level(GPIO_TPM_RST_L) && wake_on_low)
+			tpm_rst_asserted(GPIO_TPM_RST_L);
 	}
 
 	/* Trigger timer0 interrupt */
@@ -339,31 +338,31 @@ void board_configure_deep_sleep_wakepins(void)
 
 	/*
 	 * Whether it is a short pulse or long one waking on the rising edge is
-	 * fine because the goal of sys_rst is to reset the TPM and after
-	 * resuming from deep sleep the TPM will be reset. Cr50 doesn't need to
-	 * read the low value and then reset.
-	 *
-	 * Configure cr50 to resume on the rising edge of sys_rst_l
+	 * fine because the goal of the system reset signal is to reset the TPM
+	 * and after resuming from deep sleep the TPM will be reset. Cr50
+	 * doesn't need to read the low value and then reset.
 	 */
-	/* Disable sys_rst_l as a wake pin */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 0);
-	/* Reconfigure and reenable it. */
-	GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 1); /* edge sensitive */
-	GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0);  /* wake on high */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);   /* enable powerdown exit */
-
-	/*
-	 * If the board includes plt_rst_l, configure Cr50 to resume on the
-	 * rising edge of this signal.
-	 */
-	if (board_has_plt_rst()) {
-		/* Disable sys_rst_l as a wake pin */
+	if (board_use_plt_rst()) {
+		/*
+		 * If the board includes plt_rst_l, configure Cr50 to resume on
+		 * the rising edge of this signal.
+		 */
+		/* Disable plt_rst_l as a wake pin */
 		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 0);
 		/* Reconfigure and reenable it. */
 		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 1); /* edge sensitive */
 		GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 0);  /* wake on high */
 		/* enable powerdown exit */
 		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
+	} else {
+		 /* Configure cr50 to resume on the rising edge of sys_rst_l */
+		/* Disable sys_rst_l as a wake pin */
+		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 0);
+		/* Reconfigure and reenable it. */
+		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 1); /* edge sensitive */
+		GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0);  /* wake on high */
+		/* enable powerdown exit */
+		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
 	}
 }
 
@@ -388,10 +387,16 @@ static void configure_board_specific_gpios(void)
 	if (board_rst_pullup_needed())
 		GWRITE_FIELD(PINMUX, DIOM0_CTL, PU, 1);
 
-	/* Connect PLT_RST_L signal to the pinmux */
-	if (board_has_plt_rst()) {
-		/* Signal using GPIO1 pin 10 for DIOA13 */
-		GWRITE(PINMUX, GPIO1_GPIO10_SEL, GC_PINMUX_DIOM3_SEL);
+	/*
+	 * Connect either plt_rst_l or sys_rst_l to GPIO_TPM_RST_L based on the
+	 * board type. This signal is used to monitor AP resets and reset the
+	 * TPM.
+	 *
+	 * plt_rst_l is on diom3, and sys_rst_l is on diom0.
+	 */
+	if (board_use_plt_rst()) {
+		/* Use plt_rst_l as the tpm reset signal. */
+		GWRITE(PINMUX, GPIO1_GPIO0_SEL, GC_PINMUX_DIOM3_SEL);
 		/* Enbale the input */
 		GWRITE_FIELD(PINMUX, DIOM3_CTL, IE, 1);
 
@@ -402,6 +407,19 @@ static void configure_board_specific_gpios(void)
 		GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1);
 		/* Enable powerdown exit on DIOM3 */
 		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
+	} else {
+		/* Use sys_rst_l as the tpm reset signal. */
+		GWRITE(PINMUX, GPIO1_GPIO0_SEL, GC_PINMUX_DIOM0_SEL);
+		/* Enbale the input */
+		GWRITE_FIELD(PINMUX, DIOM0_CTL, IE, 1);
+
+		/* Set power down for the equivalent of DIO_WAKE_FALLING */
+		/* Set to be edge sensitive */
+		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 1);
+		/* Select failling edge polarity */
+		GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 1);
+		/* Enable powerdown exit on DIOM0 */
+		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
 	}
 }
 
@@ -511,8 +529,8 @@ int flash_regions_to_enable(struct g_flash_region *regions,
 	return 3;
 }
 
-/* This is the interrupt handler to react to SYS_RST_L_IN */
-void sys_rst_asserted(enum gpio_signal signal)
+/* This is the interrupt handler to react to TPM_RST_L */
+void tpm_rst_asserted(enum gpio_signal signal)
 {
 	/*
 	 * Cr50 drives SYS_RST_L in certain scenarios, in those cases
diff --git a/board/cr50/board.h b/board/cr50/board.h
index df1e447542..c5d11a196f 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -157,7 +157,7 @@ enum usb_spi {
 
 void board_configure_deep_sleep_wakepins(void);
 /* Interrupt handler */
-void sys_rst_asserted(enum gpio_signal signal);
+void tpm_rst_asserted(enum gpio_signal signal);
 void device_state_on(enum gpio_signal signal);
 void post_reboot_request(void);
 
@@ -170,7 +170,7 @@ void deassert_ec_rst(void);
 int is_ec_rst_asserted(void);
 
 int board_has_ap_usb(void);
-int board_has_plt_rst(void);
+int board_use_plt_rst(void);
 int board_rst_pullup_needed(void);
 int board_tpm_uses_i2c(void);
 int board_tpm_uses_spi(void);
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index cf87fcf2e8..f279bf7cf9 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -8,12 +8,17 @@
  * Note: Those with interrupt handlers must be declared first. */
 
 /*
- * We can assert SYS_RST_L but so can the EC, so we need react if it's pulled
- * low. The ARM core can't trigger an interrupt if it's driving it as an output
- * so we attach two internal GPIOs to the same pad.
+ * The system reset signal can be from two different pins depending on what the
+ * board type is. One board uses plt_rst_l (diom3) and the other board type uses
+ * sys_rst_l (diom0) to detect a warm reset. The pin is selected based on the
+ * board properties in board.c
+ *
+ * On both boards sys_rst_l is used as an output to trigger warm resets. The ARM
+ * core can't trigger an interrupt if it's driving it as an output so we attach
+ * two internal GPIOs to the same pad if sys_rst_l is also being used to detect
+ * system resets.
  */
-GPIO_INT(SYS_RST_L_IN,    PIN(1, 0),  GPIO_INT_FALLING, sys_rst_asserted)
-GPIO_INT(PLT_RST_L,       PIN(1, 10), GPIO_INT_FALLING, sys_rst_asserted)
+GPIO_INT(TPM_RST_L,       PIN(1, 0),  GPIO_INT_FALLING, tpm_rst_asserted)
 GPIO_INT(DETECT_AP,       PIN(1, 1),  GPIO_INT_HIGH, device_state_on)
 GPIO_INT(DETECT_EC,       PIN(1, 2),  GPIO_INT_HIGH, device_state_on)
 GPIO_INT(DETECT_SERVO,    PIN(1, 3),  GPIO_INT_HIGH | GPIO_PULL_DOWN,
@@ -69,7 +74,10 @@ PINMUX(GPIO(INT_AP_L),        A5, DIO_INPUT)	/* DIOB7 is p_digitial_od */
 PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT)
 PINMUX(GPIO(AP_FLASH_SELECT), B3, DIO_INPUT)
 PINMUX(GPIO(EN_PP3300_INA_L), B7, DIO_INPUT)
-PINMUX(GPIO(SYS_RST_L_IN),    M0, DIO_WAKE_FALLING)
+/*
+ * To allow the EC to drive the signal we set sys_rst_l_out as an input here and
+ * only change it to an output when we want to assert the signal.
+ */
 PINMUX(GPIO(SYS_RST_L_OUT),   M0, DIO_INPUT)
 PINMUX(GPIO(CCD_MODE_L),      M1, DIO_INPUT)
 PINMUX(GPIO(BATT_PRES_L),     M2, 0)
diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h
index b0c3a12431..6fc8b798fc 100644
--- a/board/cr50/scratch_reg1.h
+++ b/board/cr50/scratch_reg1.h
@@ -23,7 +23,9 @@
 
 /* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
 #define BOARD_NEEDS_SYS_RST_PULL_UP  (1 << 5)   /* Add a pullup to sys_rst_l */
-#define BOARD_USE_PLT_RESET          (1 << 6)   /* Platform reset exists */
+#define BOARD_USE_PLT_RESET          (1 << 6)   /* Use plt_rst_l instead of */
+						/* sys_rst_l to monitor the */
+						/* system resets */
 
 /*
  * Bits to store console and write protect bit states across deep sleep and