diff options
author | Rong Chang <rongchang@google.com> | 2017-02-22 11:32:39 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-27 16:56:24 -0800 |
commit | ec98dbfb35bb22bb6b9096eceedda93c9f88f85c (patch) | |
tree | 17a36638e971abafe0ad4b7a452a2078f47a67e4 | |
parent | 31cfc63b80ea8f5b778e6c3f568f325a6064244a (diff) | |
download | chrome-ec-ec98dbfb35bb22bb6b9096eceedda93c9f88f85c.tar.gz |
stm32f09x: fix flash protection offset
STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB),
which doesn't fit the layout requirement in config_std_internal_flash.h.
This CL hardcodes the layout and flash bank mapping.
BUG=chrome-os-partner:62372
BUG=chromium:694972
TEST=load on elm and manually enable write protect using flashrom
# flashrom -p ec:dev=0 --wp-enable
check ec console write protect option bytes, bank 31 is writable
> rw 0x1ffff808
read 0x1ffff808 = 0xff00ff00
> rw 0x1ffff80c
read 0x1ffff80c = 0x7f80ff00
BRANCH=oak
Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446176
-rw-r--r-- | board/elm/board.h | 24 | ||||
-rw-r--r-- | chip/stm32/config-stm32f09x.h | 59 | ||||
-rw-r--r-- | chip/stm32/config_chip.h | 2 | ||||
-rw-r--r-- | include/flash.h | 8 |
4 files changed, 91 insertions, 2 deletions
diff --git a/board/elm/board.h b/board/elm/board.h index f143dc614a..ea2452c34a 100644 --- a/board/elm/board.h +++ b/board/elm/board.h @@ -124,6 +124,30 @@ #define CONFIG_CMD_I2C_PROTECT #define CONFIG_CMD_PD_CONTROL +/* + * Flash layout: + * PSTATE(4KB) + * | + * (124KB) v (132KB) + * |<-----Protected Region------>|<------Unprotected Region----->| + * |<--------RO image--------->| | |<--------RW image----------->| + * 0 (120KB) ^ ^ (128KB) + * | | + * | sector 31(132KB sector) + * | + * sector 30(4KB sector) + */ +#undef CONFIG_RW_MEM_OFF +#undef CONFIG_RW_SIZE +#undef CONFIG_EC_WRITABLE_STORAGE_OFF +#undef CONFIG_EC_WRITABLE_STORAGE_SIZE +#undef CONFIG_WP_STORAGE_SIZE +#define CONFIG_RW_MEM_OFF (128 * 1024) +#define CONFIG_RW_SIZE (128 * 1024) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (128 * 1024) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (128 * 1024) +#define CONFIG_WP_STORAGE_SIZE (128 * 1024) + /* Drivers */ #ifndef __ASSEMBLER__ diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h index cfd57e1bf9..3da8a342f2 100644 --- a/chip/stm32/config-stm32f09x.h +++ b/chip/stm32/config-stm32f09x.h @@ -4,8 +4,12 @@ */ /* Memory mapping */ +/* + * Flash physical size: 256KB + * Write protect sectors: 31 4KB sectors, one 132KB sector + */ #define CONFIG_FLASH_SIZE 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x2000 +#define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,3 +21,56 @@ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 + +/* + * STM32F09x flash layout: + * - RO image starts at the beginning of flash: sector 0 ~ 29 + * - PSTATE immediately follows the RO image: sector 30 + * - RW image starts at 0x1f00: sector 31 + * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30 + * - Unprotected region consists of second half of RW image + * + * PSTATE(4KB) + * | + * (124KB) v (132KB) + * |<-----Protected Region------>|<------Unprotected Region----->| + * |<--------RO image--------->| |<----------RW image----------->| + * 0 (120KB) ^ ^ + * | | + * | 31(132KB sector) + * | + * 30 + * + */ + +#define _SECTOR_4KB (4 * 1024) +#define _SECTOR_132KB (132 * 1024) + +/* The EC uses one sector to emulate persistent state */ +#define CONFIG_FLASH_PSTATE +#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB +#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) + +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) +#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE _SECTOR_132KB + +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE - \ + CONFIG_EC_WRITABLE_STORAGE_OFF) + +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE + +/* We map each write protect sector to a bank */ +#define PHYSICAL_BANKS 32 +#define WP_BANK_COUNT 31 +#define PSTATE_BANK 30 +#define PSTATE_BANK_COUNT 1 + diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 0b79153113..2253639f83 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -67,7 +67,7 @@ /* Program is run directly from storage */ #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE -#if !defined(CHIP_VARIANT_STM32F446) +#if !defined(CHIP_VARIANT_STM32F446) && !defined(CHIP_VARIANT_STM32F09X) /* Compute the rest of the flash params from these */ #include "config_std_internal_flash.h" #endif diff --git a/include/flash.h b/include/flash.h index 2d50708f8a..5963020c8a 100644 --- a/include/flash.h +++ b/include/flash.h @@ -16,16 +16,24 @@ * TODO(crosbug.com/p/62372): This assumes flash protection blocks are all of * identical sizes, which is incorrect, for example, on STM32F091VC. */ +#ifndef PHYSICAL_BANKS #define PHYSICAL_BANKS (CONFIG_FLASH_SIZE / CONFIG_FLASH_BANK_SIZE) +#endif /* WP region offset and size in units of flash banks */ #define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE) +#ifndef WP_BANK_COUNT #define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE) +#endif /* Persistent protection state flash offset / size / bank */ #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK) +#ifndef PSTATE_BANK #define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE) +#endif +#ifndef PSTATE_BANK_COUNT #define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE) +#endif #else #define PSTATE_BANK_COUNT 0 #endif |