g:sps: do not stall reset when CS is asserted

Stalling reset during when CS is asserted is useful to start with, it
was added before out of abundance of caution, but come to think of it,
should the reset happen asynchronously driven be the EC, the AP would
be reset too. And when AP is reset on its own accord, it would not be
transmitting anything on the SPI interface.

On top of that it turns out that in some cases reset on ARM platforms
is accompanied by the CS line driven low, which causes infinite loop
if Cr50 is waiting for CS to deassert before proceeding.

BRANCH=cr50
BUG=b:67008109
TEST=verified that RMA reset operates properly on both ARM and x86
     platforms.

Change-Id: I43efd0cefa5d6eb543dfd27e3c9fb3b4bf1a8ea6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/791818
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>

1 files changed, 0 insertions, 14 deletions

diff --git a/chip/g/sps.c b/chip/g/sps.c
index 76b4d4d462..206f435e66 100644
--- a/chip/g/sps.c
+++ b/chip/g/sps.c
@@ -194,20 +194,6 @@ static void sps_configure(enum sps_mode mode, enum spi_clock_mode clk_mode,
 	/* xfer 0xff when tx fifo is empty */
 	GREG32(SPS, DUMMY_WORD) = GC_SPS_DUMMY_WORD_DEFAULT;
 
-	if (sps_cs_asserted()) {
-		/*
-		 * Reset while the external controller is mid SPI
-		 * transaction.
-		 */
-		ccprintf("%s: reset while CS active\n", __func__);
-		/*
-		 * Wait for external controller to deassert CS before
-		 * continuing.
-		 */
-		while (sps_cs_asserted())
-			;
-	}
-
 	/* [5,4,3]           [2,1,0]
 	 * RX{DIS, EN, RST} TX{DIS, EN, RST}
 	 */