yorp: initial add of octopus BOM-A board

BRANCH=none
BUG=b:73811887
TEST=build yorp and all other boards

Change-Id: I2c29ba86f29a3d25128c00c1b55e90f6843bcdd5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/935367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 117 insertions, 0 deletions

diff --git a/board/yorp/board.c b/board/yorp/board.c
new file mode 100644
index 0000000000..b44483a0e1
--- /dev/null
+++ b/board/yorp/board.c
@@ -0,0 +1,22 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Yorp board-specific configuration */
+
+#include "common.h"
+#include "gpio.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+/* TODO(b/73811887): Fill out correctly */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/board/yorp/board.h b/board/yorp/board.h
new file mode 100644
index 0000000000..191085aab5
--- /dev/null
+++ b/board/yorp/board.h
@@ -0,0 +1,40 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Yorp board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Optional features */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2    0  /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
+#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+
+/* Internal SPI flash on NPCX7 */
+/* Flash is 1MB but reserve half for future use. */
+#define CONFIG_FLASH_SIZE (512 * 1024)
+
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q128 /* Internal SPI flash type. */
+
+#define CONFIG_POWER_BUTTON
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* TODO(b/73811887): Fill out correctly */
+enum adc_channel {
+	ADC_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/yorp/build.mk b/board/yorp/build.mk
new file mode 100644
index 0000000000..8c11d2f43e
--- /dev/null
+++ b/board/yorp/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6f
+
+board-y=board.o
\ No newline at end of file
diff --git a/board/yorp/ec.tasklist b/board/yorp/ec.tasklist
new file mode 100644
index 0000000000..c4cbb43a33
--- /dev/null
+++ b/board/yorp/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
new file mode 100644
index 0000000000..c937d02c36
--- /dev/null
+++ b/board/yorp/gpio.inc
@@ -0,0 +1,15 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
+GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
+
+
+GPIO(ENTERING_RW,		PIN(8, 0), GPIO_OUT_LOW)			/* EC Entering RW */
\ No newline at end of file
diff --git a/util/flash_ec b/util/flash_ec
index bc3bd0b656..211a089be3 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -131,6 +131,7 @@ BOARDS_NPCX_SPI=(
 BOARDS_NPCX_INT_SPI=(
 	grunt
 	meowth
+	yorp
 	zoombini
 )