diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-02-25 17:52:22 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-26 09:32:52 -0800 |
| commit | fb8e3f922b2b0c72c1f26e140dc3733b9efbf24c (patch) | |
| tree | 4ebf177c6352bdaac4a261c7a9d573575f6ade1e | |
| parent | e5e1b7ea5dbc6a22e14c63ef9a6c4f00cfd1993f (diff) | |
| download | chrome-ec-fb8e3f922b2b0c72c1f26e140dc3733b9efbf24c.tar.gz | |
stm32: trigger watchdog hard reset immediately
When using the watchdog (IWDG) to perform the cold reset, set the Key
register to 'RELOAD' (0xAAAA) rather than 'START' (0xCCCC) to ensure
that the reset is performed immediately rather than at the end of the
current watchdog period (which might be 1 to 5s away).
Replace the Key register special values by their symbolic constants.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=On ZerbleBarn using a STM32H7, run 'ectool reboot_ec cold' and see
the MCU rebooting immediately rather than after 5s.
Change-Id: Ib49c703e3ec973389e4d774eda53f3be7ec4dd2e
Reviewed-on: https://chromium-review.googlesource.com/936764
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | chip/stm32/system.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index ceb19089ed..396fcac964 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -388,9 +388,9 @@ void system_reset(int flags) STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; #else /* Ask the watchdog to trigger a hard reboot */ - STM32_IWDG_KR = 0x5555; + STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; STM32_IWDG_RLR = 0x1; - STM32_IWDG_KR = 0xcccc; + STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; #endif /* wait for the chip to reboot */ while (1) |