diff options
| author | Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> | 2018-05-15 15:00:42 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-05-22 15:54:11 -0700 |
| commit | 2c9c55da93f57ac8eaef47328239d8957fd4a5d6 (patch) | |
| tree | 348f0db9253c9e8e5a09e185392f6462e2676a66 | |
| parent | 32b1e3add72159df481ea5e3d86b581ef07caaa3 (diff) | |
| download | chrome-ec-2c9c55da93f57ac8eaef47328239d8957fd4a5d6.tar.gz | |
octopus: implement device mode
To enable device mode, set the gpio USB2_OTG_ID
in the respective boards to high.
Pull the gpio low to disable device mode.
BUG=b:79343083
BRANCH=NONE
TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high,
for DFP mode gpio USB2_OTG_ID should be low.
In OS console, lspci should list xdci.
(with chromiumos/third_party/coreboot/+/1064592)
Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1058832
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | baseboard/octopus/baseboard.h | 1 | ||||
| -rw-r--r-- | baseboard/octopus/usb_pd_policy.c | 4 | ||||
| -rw-r--r-- | board/bip/gpio.inc | 1 | ||||
| -rw-r--r-- | board/phaser/gpio.inc | 1 | ||||
| -rw-r--r-- | board/yorp/gpio.inc | 2 |
5 files changed, 7 insertions, 2 deletions
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index 06acea5f97..9bc515759e 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -175,7 +175,6 @@ #define CONFIG_USB_PD_DISCHARGE_PPC #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USBC_SS_MUX -#define CONFIG_USBC_SS_MUX_DFP_ONLY #define CONFIG_USBC_VCONN #define CONFIG_USBC_VCONN_SWAP #define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c index 6c90a53d56..1daf344328 100644 --- a/baseboard/octopus/usb_pd_policy.c +++ b/baseboard/octopus/usb_pd_policy.c @@ -105,7 +105,9 @@ int pd_check_vconn_swap(int port) void pd_execute_data_swap(int port, int data_role) { - /* Do nothing */ + /* On Octopus, only the first port can act as OTG */ + if (port == 0) + gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP)); } int pd_is_valid_input_voltage(int mv) diff --git a/board/bip/gpio.inc b/board/bip/gpio.inc index 301861ae81..7e66e23afc 100644 --- a/board/bip/gpio.inc +++ b/board/bip/gpio.inc @@ -95,6 +95,7 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(A, 1), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C0_BC12_VBUS_ON, PIN(J, 4), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C1_BC12_VBUS_ON, PIN(J, 5), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_PD_RST_ODL, PIN(L, 7), GPIO_ODR_HIGH) /* C1 PD Reset */ +GPIO(USB2_OTG_ID, PIN(I, 2), GPIO_OUT_LOW) /* OTG ID */ /* Alternate functions GPIO definitions */ /* Cr50 requires no pull-ups on UART pins. */ diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index 60b151e2cc..3d4d8a78ec 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -109,6 +109,7 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) +GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_OUT_LOW) /* OTG ID */ /* LED */ GPIO(BAT_LED_ORANGE_L, PIN(C, 3), GPIO_OUT_HIGH) /* LED_1_L */ diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index ec4e084bd3..8ce745de0b 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -99,6 +99,8 @@ GPIO(I2C7_SDA, PIN(B, 2), GPIO_INPUT | /* USB pins */ GPIO(EN_USB_A_5V, PIN(6, 7), GPIO_OUT_LOW) /* Enable A0/A1 5V Charging */ +/* OTG pin - This pin will be changed to PIN(8,3) in Proto 2*/ +GPIO(USB2_OTG_ID, PIN(A, 0), GPIO_OUT_LOW) /* OTG ID */ GPIO(USB_A_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0/A1 1.5A Charging */ /* TODO(b/74254366): Break out A1 signals once they are there in HW */ /* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ |