ish: move REG32 macros for interrupt control into header files

This is a good portion of the fixes needed for b:130573158, but we
still have the HECI registers to deal with. I have those in a separate
CL as they were giving me a significant amount of trouble.

BUG=b:130573158
BRANCH=none
TEST=arcada_ish is functioning as normal after changes

Change-Id: I9c209a329d61f7f55c260006cdffbfc705521195
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1586458
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1598521
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>

6 files changed, 81 insertions, 76 deletions

diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index 374497b1ba..4bfd6fcab4 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -85,8 +85,8 @@ static void pmu_wakeup_isr(void)
 	 * Indicate completion of servicing the interrupt to IOAPIC first
 	 * then indicate completion of servicing the interrupt to LAPIC
 	 */
-	REG32(IOAPIC_EOI_REG) = ISH_PMU_WAKEUP_VEC;
-	REG32(LAPIC_EOI_REG) = 0x0;
+	IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC;
+	LAPIC_EOI_REG = 0x0;
 
 	__asm__ volatile ("iret;");
 
@@ -105,8 +105,8 @@ static void reset_prep_isr(void)
 	 * Indicate completion of servicing the interrupt to IOAPIC first
 	 * then indicate completion of servicing the interrupt to LAPIC
 	 */
-	REG32(IOAPIC_EOI_REG) = ISH_RESET_PREP_VEC;
-	REG32(LAPIC_EOI_REG) = 0x0;
+	IOAPIC_EOI_REG = ISH_RESET_PREP_VEC;
+	LAPIC_EOI_REG = 0x0;
 
 	handle_reset(ISH_PM_STATE_RESET_PREP);
 
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index 467d0bc55d..11b2ba3c3f 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -676,8 +676,8 @@ static void reset_prep_isr(void)
 	 * Indicate completion of servicing the interrupt to IOAPIC first
 	 * then indicate completion of servicing the interrupt to LAPIC
 	 */
-	REG32(IOAPIC_EOI_REG) = ISH_RESET_PREP_VEC;
-	REG32(LAPIC_EOI_REG) = 0x0;
+	IOAPIC_EOI_REG = ISH_RESET_PREP_VEC;
+	LAPIC_EOI_REG = 0x0;
 
 	if (pm_ctx.aon_valid) {
 		handle_reset_in_aontask(ISH_PM_STATE_RESET_PREP);
@@ -708,8 +708,8 @@ static void handle_d3(uint32_t irq_vec)
 		 * first then indicate completion of servicing the interrupt
 		 * to LAPIC
 		 */
-		REG32(IOAPIC_EOI_REG) = irq_vec;
-		REG32(LAPIC_EOI_REG) = 0x0;
+		IOAPIC_EOI_REG = irq_vec;
+		LAPIC_EOI_REG = 0x0;
 
 		pm_ctx.aon_share->pm_state = ISH_PM_STATE_D3;
 
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 03aac276fb..7e6b580d76 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -282,46 +282,50 @@ enum ish_i2c_port {
 #define CCU_SRECC_RST	BIT(3)  /* Used to indicate SRAM ECC reset */
 
 /* Fabric Agent Status register */
-#define FABRIC_AGENT_STATUS               REG32(ISH_OCP_BASE + 0x7828)
-#define FABRIC_INBAND_ERR_SECONDARY_BIT   BIT(29)
-#define FABRIC_INBAND_ERR_PRIMARY_BIT     BIT(28)
-#define FABRIC_M_ERR_BIT                  BIT(24)
+#define FABRIC_AGENT_STATUS		REG32(ISH_OCP_BASE + 0x7828)
+#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29)
+#define FABRIC_INBAND_ERR_PRIMARY_BIT	BIT(28)
+#define FABRIC_M_ERR_BIT		BIT(24)
 #define FABRIC_MIA_STATUS_BIT_ERR	(FABRIC_INBAND_ERR_SECONDARY_BIT | \
-					FABRIC_INBAND_ERR_PRIMARY_BIT | \
-					FABRIC_M_ERR_BIT)
+					 FABRIC_INBAND_ERR_PRIMARY_BIT | \
+					 FABRIC_M_ERR_BIT)
 
 /* CSME Registers */
-#define ISH_RST_REG		REG32(ISH_IPC_BASE + 0x44)
+#define ISH_RST_REG			REG32(ISH_IPC_BASE + 0x44)
 
 /* IOAPIC registers */
-#define IOAPIC_IDX        0xFEC00000
-#define IOAPIC_WDW        0xFEC00010
-#define IOAPIC_EOI_REG    0xFEC00040
-
-#define IOAPIC_VERSION               0x1
-#define IOAPIC_IOREDTBL              0x10
-#define IOAPIC_REDTBL_DELMOD_FIXED   0x00000000
-#define IOAPIC_REDTBL_DESTMOD_PHYS   0x00000000
-#define IOAPIC_REDTBL_INTPOL_HIGH    0x00000000
-#define IOAPIC_REDTBL_INTPOL_LOW     0x00002000
-#define IOAPIC_REDTBL_IRR            0x00004000
-#define IOAPIC_REDTBL_TRIGGER_EDGE   0x00000000
-#define IOAPIC_REDTBL_TRIGGER_LEVEL  0x00008000
-#define IOAPIC_REDTBL_MASK           0x00010000
+#define IOAPIC_IDX			REG32(ISH_IOAPIC_BASE + 0x0)
+#define IOAPIC_WDW			REG32(ISH_IOAPIC_BASE + 0x10)
+/* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */
+#define IOAPIC_EOI_REG_ADDR		0xFEC00040
+#define IOAPIC_EOI_REG			REG32(IOAPIC_EOI_REG_ADDR)
+
+#define IOAPIC_VERSION			(0x1)
+#define IOAPIC_IOREDTBL		(0x10)
+#define IOAPIC_REDTBL_DELMOD_FIXED	(0x00000000)
+#define IOAPIC_REDTBL_DESTMOD_PHYS	(0x00000000)
+#define IOAPIC_REDTBL_INTPOL_HIGH	(0x00000000)
+#define IOAPIC_REDTBL_INTPOL_LOW	(0x00002000)
+#define IOAPIC_REDTBL_IRR		(0x00004000)
+#define IOAPIC_REDTBL_TRIGGER_EDGE	(0x00000000)
+#define IOAPIC_REDTBL_TRIGGER_LEVEL	(0x00008000)
+#define IOAPIC_REDTBL_MASK		(0x00010000)
 
 /* WDT (Watchdog Timer) Registers */
-#define WDT_CONTROL		REG32(ISH_WDT_BASE + 0x0)
-#define WDT_RELOAD		REG32(ISH_WDT_BASE + 0x4)
-#define WDT_VALUES		REG32(ISH_WDT_BASE + 0x8)
-#define WDT_CONTROL_ENABLE_BIT	BIT(17)
+#define WDT_CONTROL			REG32(ISH_WDT_BASE + 0x0)
+#define WDT_RELOAD			REG32(ISH_WDT_BASE + 0x4)
+#define WDT_VALUES			REG32(ISH_WDT_BASE + 0x8)
+#define WDT_CONTROL_ENABLE_BIT		BIT(17)
 
 /* LAPIC registers */
-#define LAPIC_EOI_REG   0xFEE000B0
-#define LAPIC_ISR_REG   0xFEE00170
-#define LAPIC_IRR_REG   (ISH_LAPIC_BASE + 0x200)
-#define LAPIC_ESR_REG   (ISH_LAPIC_BASE + 0x280)
-#define LAPIC_ERR_RECV_ILLEGAL       BIT(6)
-#define LAPIC_ICR_REG   (ISH_LAPIC_BASE + 0x300)
+/* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */
+#define LAPIC_EOI_REG_ADDR		0xFEE000B0
+#define LAPIC_EOI_REG			REG32(LAPIC_EOI_REG_ADDR)
+#define LAPIC_ISR_REG			REG32(ISH_LAPIC_BASE + 0x170)
+#define LAPIC_IRR_REG			REG32(ISH_LAPIC_BASE + 0x200)
+#define LAPIC_ESR_REG			REG32(ISH_LAPIC_BASE + 0x280)
+#define LAPIC_ERR_RECV_ILLEGAL		BIT(6)
+#define LAPIC_ICR_REG			REG32(ISH_LAPIC_BASE + 0x300)
 
 /* SRAM control registers */
 #define ISH_SRAM_CTRL_BASE		0x00500000
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c
index a08e02de90..efa07ef062 100644
--- a/core/minute-ia/interrupts.c
+++ b/core/minute-ia/interrupts.c
@@ -26,19 +26,19 @@ extern struct idt_entry __idt[NUM_VECTORS];
 /* To count the interrupt nesting depth. Usually it is not nested */
 volatile uint32_t __in_isr;
 
-void write_ioapic_reg(const uint32_t reg, const uint32_t val)
+void write_ioapic_reg(const uint8_t reg, const uint32_t val)
 {
-	REG32(IOAPIC_IDX) = (uint8_t)reg;
-	REG32(IOAPIC_WDW) = val;
+	IOAPIC_IDX = reg;
+	IOAPIC_WDW = val;
 }
 
-uint32_t read_ioapic_reg(const uint32_t reg)
+uint32_t read_ioapic_reg(const uint8_t reg)
 {
-	REG32(IOAPIC_IDX) = (uint8_t)reg;
-	return REG32(IOAPIC_WDW);
+	IOAPIC_IDX = reg;
+	return IOAPIC_WDW;
 }
 
-void set_ioapic_redtbl_raw(const unsigned irq, const uint32_t val)
+void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val)
 {
 	const uint32_t redtbl_lo = IOAPIC_IOREDTBL + 2 * irq;
 	const uint32_t redtbl_hi = redtbl_lo + 1;
@@ -272,12 +272,13 @@ DECLARE_DEFERRED(print_lpaic_lvt_error);
  * #define VEC_POS(v) ((v) & (32 - 1))
  * #define REG_POS(v) (((v) >> 5) << 4)
  */
-static inline unsigned int lapic_get_vector(uint32_t reg_base, uint32_t vector)
+static inline unsigned int lapic_get_vector(volatile uint32_t *reg_base,
+					    uint32_t vector)
 {
 	uint32_t reg_pos = (vector >> 5) << 4;
 	uint32_t vec_pos = vector & (32 - 1);
 
-	return REG32(reg_base + reg_pos) & BIT(vec_pos);
+	return reg_base[reg_pos] & BIT(vec_pos);
 }
 
 /*
@@ -298,12 +299,12 @@ static inline unsigned int lapic_get_vector(uint32_t reg_base, uint32_t vector)
  */
 void handle_lapic_lvt_error(void)
 {
-	uint32_t esr = REG32(LAPIC_ESR_REG);
+	uint32_t esr = LAPIC_ESR_REG;
 	uint32_t ioapic_redtbl, vec;
 	int irq, max_irq_entries;
 
 	/* Ack LVT ERROR exception */
-	REG32(LAPIC_ESR_REG) = 0;
+	LAPIC_ESR_REG = 0;
 
 	/*
 	 * When IOAPIC has more than 1 interrupts in remote IRR state,
@@ -323,9 +324,9 @@ void handle_lapic_lvt_error(void)
 			/* If pending interrupt is not in LAPIC, clear it. */
 			if (ioapic_redtbl & IOAPIC_REDTBL_IRR) {
 				vec = IRQ_TO_VEC(irq);
-				if (!lapic_get_vector(LAPIC_IRR_REG, vec)) {
+				if (!lapic_get_vector(&LAPIC_IRR_REG, vec)) {
 					/* End of interrupt */
-					REG32(IOAPIC_EOI_REG) = vec;
+					IOAPIC_EOI_REG = vec;
 					ioapic_pending_count++;
 				}
 			}
@@ -414,7 +415,7 @@ void init_interrupts(void)
 	set_interrupt_gate(SOFTIRQ_VECTOR, sw_irq_handler, IDT_DESC_FLAGS);
 
 	/* Setup gate for LAPIC_LVT_ERROR vector; clear any remnant error. */
-	REG32(LAPIC_ESR_REG) = 0;
+	LAPIC_ESR_REG = 0;
 	set_interrupt_gate(LAPIC_LVT_ERROR_VECTOR, _lapic_error_handler,
 			   IDT_DESC_FLAGS);
 
diff --git a/core/minute-ia/irq_handler.h b/core/minute-ia/irq_handler.h
index 1d44a577bd..3b33fbb073 100644
--- a/core/minute-ia/irq_handler.h
+++ b/core/minute-ia/irq_handler.h
@@ -35,24 +35,24 @@ struct irq_data {
  * Each irq has a irq_data structure placed in .rodata.irqs section,
  * to be used for dynamically setting up interrupt gates
  */
-#define DECLARE_IRQ_(irq, routine, vector)				       \
-	void __keep routine(void);					       \
-	void IRQ_HANDLER(irq)(void);					       \
-	__asm__ (".section .rodata.irqs\n");				       \
-	const struct irq_data __keep CONCAT4(__irq_, irq, _, routine)	       \
-	__attribute__((section(".rodata.irqs"))) = { routine,		       \
-						     IRQ_HANDLER(irq),	       \
-						     irq};		       \
-	__asm__ (							       \
-		".section .text._irq_"#irq"_handler\n"			       \
-		"_irq_"#irq"_handler:\n"				       \
-			"pusha\n"					       \
-			ASM_LOCK_PREFIX "addl  $1, __in_isr\n"		       \
-			"irq_handler_common $0 $0 $"#irq"\n"		       \
-			"movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG) "\n"    \
-			"movl $0x00, " STRINGIFY(LAPIC_EOI_REG) "\n"	       \
-			ASM_LOCK_PREFIX "subl  $1, __in_isr\n"		       \
-			"popa\n"					       \
-			"iret\n"					       \
+#define DECLARE_IRQ_(irq, routine, vector)				\
+	void __keep routine(void);					\
+	void IRQ_HANDLER(irq)(void);					\
+	__asm__ (".section .rodata.irqs\n");				\
+	const struct irq_data __keep CONCAT4(__irq_, irq, _, routine)	\
+		__attribute__((section(".rodata.irqs"))) = { routine,	\
+							     IRQ_HANDLER(irq), \
+							     irq};	\
+	__asm__ (							\
+		".section .text._irq_"#irq"_handler\n"			\
+		"_irq_"#irq"_handler:\n"				\
+		"pusha\n"						\
+		ASM_LOCK_PREFIX "addl  $1, __in_isr\n"			\
+		"irq_handler_common $0 $0 $"#irq"\n"			\
+		"movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG_ADDR) "\n" \
+		"movl $0x00, " STRINGIFY(LAPIC_EOI_REG_ADDR) "\n"	\
+		ASM_LOCK_PREFIX "subl  $1, __in_isr\n"			\
+		"popa\n"						\
+		"iret\n"						\
 		);
 #endif  /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/minute-ia/switch.S b/core/minute-ia/switch.S
index c5098b9003..f8d0be3874 100644
--- a/core/minute-ia/switch.S
+++ b/core/minute-ia/switch.S
@@ -61,9 +61,9 @@ default_int_handler:
 	cmpl $LAPIC_SPURIOUS_INT_VECTOR, %eax
 	je 1f				# No EOI for LAPIC_SPURIOUS_INT_VECTOR
 
-	movl %eax, IOAPIC_EOI_REG	# Indicate completion of servicing the
+	movl %eax, IOAPIC_EOI_REG_ADDR	# Indicate completion of servicing the
 					# interrupt to IOAPIC first
-	movl $0x00, LAPIC_EOI_REG	# Indicate completion of servicing the
+	movl $0x00, LAPIC_EOI_REG_ADDR	# Indicate completion of servicing the
 					# interrupt to LAPIC next
 	1:
 	# Ensure we balance the __in_isr counter
@@ -85,7 +85,7 @@ sw_irq_handler:
 
 	# Indicate completion of servicing the interrupt to LAPIC.
 	# No IOAPIC EOI needed as this is SW triggered.
-	movl $0x00, LAPIC_EOI_REG
+	movl $0x00, LAPIC_EOI_REG_ADDR
 
 	# Decrement ISR counter and restore general purpose registers.
 	ASM_LOCK_PREFIX subl $1, __in_isr
@@ -110,7 +110,7 @@ __switchto:
 
 	# Indicate completion of servicing the interrupt to LAPIC.
 	# No IOAPIC EOI needed as this is SW triggered.
-	movl $0x00, LAPIC_EOI_REG
+	movl $0x00, LAPIC_EOI_REG_ADDR
 
 	# Decrement ISR counter and restore general purpose registers.
 	ASM_LOCK_PREFIX subl $1, __in_isr