diff options
| author | Scott Collyer <scollyer@google.com> | 2019-05-06 14:09:17 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-24 15:10:00 -0700 |
| commit | 74924114a5b3762424aec95e009b1106714f6f9b (patch) | |
| tree | 6b57df350c2113e6eb0783bb6a74b9591ae4dbdc | |
| parent | 58e31f4788e369028f960e2fd39b435f1a1c4687 (diff) | |
| download | chrome-ec-74924114a5b3762424aec95e009b1106714f6f9b.tar.gz | |
cml: Remove while loop to check for PP5000_A_PG signal
When cometlake is sequencing from G3->S5, the 5000_A rail is
enabled. After enabling the 5000_A rail there was a while() loop to
wait for the 5000_A rail to go high. If for some reason this rail did
not go high, then it would just loop there until a watchdog reset.
This CL removes this while loop check and instead modifies the macro
CHIPSET_G3S5_POWERUP_SIGNAL to include the PP5000_A_PG signal. The
common intel_x86 power sequencing code already has a check just after
the call to chipset_pre_init_callback.
BUG=none
BRANCH=none
TEST=Manual
If no battery is present and the bq25710 reset register bit is set,
then PPVAR_VSYS gets set to ~4V which is not high enough to generate
PP5000_A rail. In this state the EC would consistently watchdog loop
when just as AP power sequencing was initiated by the EC. Verified
with this CL, that while the PP5000_A rail still doesn't come up, that
the EC no longer hits a watchdog and power signal failure is logged in
the EC console.
Change-Id: I02aab7ed4f4723ec0d3ae04e4b8093494877615f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1599674
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
| -rw-r--r-- | power/cometlake.c | 9 | ||||
| -rw-r--r-- | power/cometlake.h | 3 |
2 files changed, 7 insertions, 5 deletions
diff --git a/power/cometlake.c b/power/cometlake.c index 0c6a8243f1..ec0052ff85 100644 --- a/power/cometlake.c +++ b/power/cometlake.c @@ -93,10 +93,11 @@ void chipset_pre_init_callback(void) /* Turn on A (except PP5000_A) rails*/ gpio_set_level(GPIO_EN_A_RAILS, 1); - /* Ensure that PP5000_A rail is stable */ - while (!gpio_get_level(GPIO_PP5000_A_PG_OD)) - ; - + /* + * The status of the 5000_A rail is verifed in the calling function via + * power_wait_signals() as PP5000_A_PGOOD is included in the + * CHIPSET_G3S5_POWERUP_SIGNAL macro. + */ } enum power_state power_handle_state(enum power_state state) diff --git a/power/cometlake.h b/power/cometlake.h index e3be31bdfb..c40562da17 100644 --- a/power/cometlake.h +++ b/power/cometlake.h @@ -20,7 +20,8 @@ #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ PP5000_PGOOD_POWER_SIGNAL_MASK) -#define CHIPSET_G3S5_POWERUP_SIGNAL POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) +#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ + POWER_SIGNAL_MASK(PP5000_A_PGOOD)) #define CHARGER_INITIALIZED_DELAY_MS 100 #define CHARGER_INITIALIZED_TRIES 40 |