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| author | Dino Li <Dino.Li@ite.com.tw> | 2021-05-19 12:05:33 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-20 04:00:03 +0000 |
| commit | e51ceb7a8006998c5d3e3a6ae8508584a4dcc7db (patch) | |
| tree | acd2833c9b6213179aa5712a7fdc1537c7a00f80 | |
| parent | d72c3d718eee34020a7513d44a80bfd60ffe5e10 (diff) | |
| download | chrome-ec-e51ceb7a8006998c5d3e3a6ae8508584a4dcc7db.tar.gz | |
zephyr: shi/it8xxx2: Ensure spi chip select alt function is enabled.
BUG=b:188577674, b:180980668
BRANCH=none
TEST=boot to kernel on Asurada. (with connecting both AC and battery)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Icbcdfbad611eed4b7684c05133a4a20fed245353
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905038
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
| -rw-r--r-- | zephyr/drivers/cros_shi/cros_shi_it8xxx2.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c index 1fd3cc4e96..0c0391afe7 100644 --- a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c +++ b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c @@ -11,6 +11,8 @@ #include <kernel.h> #include <logging/log.h> #include <soc.h> +#include <drivers/pinmux.h> +#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h> #include "console.h" #include "host_command.h" @@ -258,6 +260,10 @@ static void shi_ite_int_handler(const void *arg) } +/* + * SHI init priority is behind CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY to + * overwrite GPIO_INPUT setting of spi chip select pin. + */ static int cros_shi_ite_init(const struct device *dev) { /* Set FIFO data target count */ @@ -314,13 +320,20 @@ static int cros_shi_ite_init(const struct device *dev) /* SPI slave controller enable (after settings are ready) */ IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN; +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pinmuxm), okay) + const struct device *portm = DEVICE_DT_GET(DT_NODELABEL(pinmuxm)); + + /* Ensure spi chip select alt function is enabled. */ + pinmux_pin_set(portm, 5, IT8XXX2_PINMUX_FUNC_1); +#endif + /* Enable SPI slave interrupt */ IRQ_CONNECT(DT_INST_IRQN(0), 0, shi_ite_int_handler, 0, 0); irq_enable(DT_INST_IRQN(0)); return 0; } -SYS_INIT(cros_shi_ite_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +SYS_INIT(cros_shi_ite_init, POST_KERNEL, 52); /* Get protocol information */ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) |