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| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-07-13 14:29:31 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-13 21:33:30 +0000 |
| commit | 2ac1688423a1aa43706f126bfa616fa8de092bcf (patch) | |
| tree | 501b384dce668c3f2c7f46cab54db63dab9a0d3a | |
| parent | a9b7a3d6ed8331e88d90b76f215c91d488d4c999 (diff) | |
| download | chrome-ec-2ac1688423a1aa43706f126bfa616fa8de092bcf.tar.gz | |
zephyr: implement panic register print for riscv
Implement panic register print for rv32i. This lets us see the
registers after a crash, which is very useful for debugging.
BUG=b:193552648
BRANCH=none
TEST=got a crash, see this on UART:
Fatal error: 0
ra = 0x80005864
gp = 0x8010D3C0
tp = 0x00000000
a0 = 0x00000000
a1 = 0x00000000
a2 = 0x00000000
a3 = 0x00000000
a4 = 0x80107FC0
a5 = 0x00000500
a6 = 0x00000000
a7 = 0xAAAAAAAA
t0 = 0x00000000
t1 = 0x8010D298
t2 = 0x435F4450
t3 = 0x00000030
t4 = 0x00000000
t5 = 0x00000000
t6 = 0x00000000
mepc = 0xFFFFFFF4
mstatus = 0x00001880
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I5b91276d274f5792ff6b9136adc319d03ed6dbb3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3024958
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
| -rw-r--r-- | zephyr/shim/src/panic.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c index 7fa401c3b1..73889565f9 100644 --- a/zephyr/shim/src/panic.c +++ b/zephyr/shim/src/panic.c @@ -25,7 +25,7 @@ * - human readable name */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) #define PANIC_ARCH PANIC_ARCH_CORTEX_M #define PANIC_REG_LIST(M) \ M(basic.r0, cm.frame[0], a1) \ @@ -39,6 +39,32 @@ #define PANIC_REG_EXCEPTION(pdata) pdata->cm.regs[1] #define PANIC_REG_REASON(pdata) pdata->cm.regs[3] #define PANIC_REG_INFO(pdata) pdata->cm.regs[4] +#elif defined(CONFIG_RISCV) && !defined(CONFIG_64BIT) +#define PANIC_ARCH PANIC_ARCH_RISCV_RV32I +#define PANIC_REG_LIST(M) \ + M(ra, riscv.regs[1], ra) \ + M(gp, riscv.regs[2], gp) \ + M(tp, riscv.regs[3], tp) \ + M(a0, riscv.regs[4], a0) \ + M(a1, riscv.regs[5], a1) \ + M(a2, riscv.regs[6], a2) \ + M(a3, riscv.regs[7], a3) \ + M(a4, riscv.regs[8], a4) \ + M(a5, riscv.regs[9], a5) \ + M(a6, riscv.regs[10], a6) \ + M(a7, riscv.regs[11], a7) \ + M(t0, riscv.regs[12], t0) \ + M(t1, riscv.regs[13], t1) \ + M(t2, riscv.regs[14], t2) \ + M(t3, riscv.regs[15], t3) \ + M(t4, riscv.regs[16], t4) \ + M(t5, riscv.regs[17], t5) \ + M(t6, riscv.regs[18], t6) \ + M(mepc, riscv.mepc, mepc) \ + M(mstatus, riscv.mcause, mstatus) +#define PANIC_REG_EXCEPTION(pdata) (pdata->riscv.mcause) +#define PANIC_REG_REASON(pdata) (pdata->riscv.regs[11]) +#define PANIC_REG_INFO(pdata) (pdata->riscv.regs[10]) #else /* Not implemented for this arch */ #define PANIC_ARCH 0 |