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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2018-11-27 11:14:33 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-12-05 01:13:29 -0800
commitb91e34ca6bc7f3c5dae282eec5c2845ff5ec5b52 (patch)
tree89cb1aa0d58eb67f6702f0ff5abc6b850116a0a1
parent1caaa593b1abee713a6d5b30ac3c20a6713ddf76 (diff)
downloadchrome-ec-b91e34ca6bc7f3c5dae282eec5c2845ff5ec5b52.tar.gz
gpio: Add configuration for EC_PCH_RTCRST GPIO in octopus boards
This will help with using the hardware support to reset the RTC on the SoC. BUG=b:119678692 BRANCH=octopus TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to trigger an RTC reset and ensure that EC does not get reset while the SoC boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and wake from ec hibernate (10 iterations each) and suspend_stress_test for 50 iterations successfully. Change-Id: Ib79012b43e397d4c27ca829b135115bebf77dedb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1354493 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat
-rw-r--r--board/ampton/gpio.inc2
-rw-r--r--board/bip/gpio.inc2
-rw-r--r--board/bobba/gpio.inc1
-rw-r--r--board/casta/gpio.inc3
-rw-r--r--board/fleex/gpio.inc1
-rw-r--r--board/meep/gpio.inc2
-rw-r--r--board/phaser/gpio.inc1
-rw-r--r--board/yorp/gpio.inc1
8 files changed, 9 insertions, 4 deletions
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc
index 2988ed44b0..e79acaccba 100644
--- a/board/ampton/gpio.inc
+++ b/board/ampton/gpio.inc
@@ -46,6 +46,7 @@ GPIO(LID_ACCEL_INT_L, PIN(J, 3), GPIO_INPUT | GPIO_SEL_1P8V)
GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT) /* PLT_RST_L: Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(K, 7), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(C, 5), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(D, 1), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
@@ -58,7 +59,6 @@ GPIO(PP3300_PG, PIN(K, 1), GPIO_INPUT) /* PP3300_PG_OD */
GPIO(PMIC_EN, PIN(D, 7), GPIO_OUT_LOW) /* Enable A Rails via PMIC */
GPIO(PCH_RSMRST_L, PIN(C, 6), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */
GPIO(PCH_SYS_PWROK, PIN(K, 4), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */
-GPIO(PCH_RTCRST, PIN(K, 7), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
/* Peripheral rails */
GPIO(ENABLE_BACKLIGHT, PIN(B, 5), GPIO_ODR_HIGH |
diff --git a/board/bip/gpio.inc b/board/bip/gpio.inc
index 80da333636..eca5c54bce 100644
--- a/board/bip/gpio.inc
+++ b/board/bip/gpio.inc
@@ -42,6 +42,8 @@ GPIO_INT(TABLET_MODE_L, PIN(H, 4), GPIO_INT_BOTH, hall_sensor_isr)
GPIO(PCH_PLTRST_L, PIN(E, 3), GPIO_INPUT) /* PLT_RST_L: Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(B, 6), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(K, 7), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
+
/*
* TODO(b/76023457): Move below 2 signals to virtual wires over eSPI
*/
diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc
index 3bbb5598e9..b36cf41cea 100644
--- a/board/bobba/gpio.inc
+++ b/board/bobba/gpio.inc
@@ -53,6 +53,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
diff --git a/board/casta/gpio.inc b/board/casta/gpio.inc
index 00597e5270..f3e5e04f48 100644
--- a/board/casta/gpio.inc
+++ b/board/casta/gpio.inc
@@ -50,6 +50,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
@@ -91,8 +92,6 @@ GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
*/
GPIO(CPU_PROCHOT, PIN(3, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* PCH_PROCHOT_ODL */
-GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
-
/* I2C pins - Alternate function below configures I2C module on these pins */
GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SCL */
GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) /* EC_I2C_BATTERY_3V3_SDA */
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
index e20a6ed4b9..92e730248b 100644
--- a/board/fleex/gpio.inc
+++ b/board/fleex/gpio.inc
@@ -53,6 +53,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc
index a642f47fc4..a24f26a5cd 100644
--- a/board/meep/gpio.inc
+++ b/board/meep/gpio.inc
@@ -56,6 +56,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
@@ -68,7 +69,6 @@ GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */
GPIO(PMIC_EN, PIN(7, 2), GPIO_OUT_LOW) /* Enable A Rails via PMIC */
GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */
GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */
-GPIO(PCH_RTCRST, PIN(7, 6), GPIO_INPUT) /* EC_PCH_RTCRST */
/* Peripheral rails */
GPIO(ENABLE_BACKLIGHT, PIN(D, 3), GPIO_ODR_HIGH |
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
index 9a65594c4b..11c1bfde0b 100644
--- a/board/phaser/gpio.inc
+++ b/board/phaser/gpio.inc
@@ -56,6 +56,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
index b944997a93..38a491202e 100644
--- a/board/yorp/gpio.inc
+++ b/board/yorp/gpio.inc
@@ -54,6 +54,7 @@ GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) /* SLP_S0_L */
*/
GPIO(PLT_RST_L, PIN(C, 7), GPIO_INPUT) /* Platform Reset from SoC */
GPIO(SYS_RESET_L, PIN(3, 4), GPIO_ODR_HIGH) /* SYS_RST_ODL */
+GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC_ENTERING_RW */
GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
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