cleanup: Rename geometry constants

Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
author: Shawn Nematbakhsh <shawnn@chromium.org> 2015-09-04 19:09:33 -0700
committer: chrome-bot <chrome-bot@chromium.org> 2015-09-16 14:49:31 -0700
commit: d58e54730c03290296df5bb65cb84264e4b2facc (patch)
tree: d736570c84a0e9737b8881ec68b073327a5c2ae5
parent: 4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff)
download: chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz
42 files changed, 123 insertions, 99 deletions
diff --git a/Makefile b/Makefile
index 9d5437c876..04ab728222 100644
--- a/Makefile
+++ b/Makefile
@@ -108,9 +108,10 @@ _rw_off:=$(shell echo "$$(($(_rw_off_str)))")
 _rw_size_str:=$(shell echo "CONFIG_RW_SIZE" | $(CPP) $(CPPFLAGS) -P \
 		-Ichip/$(CHIP) -I$(BDIR) -imacros include/config.h)
 _rw_size:=$(shell echo "$$(($(_rw_size_str)))")
-_flash_base_str:=$(shell echo "CONFIG_FLASH_BASE" | $(CPP) $(CPPFLAGS) -P \
+_program_memory_base_str:=$(shell echo "CONFIG_PROGRAM_MEMORY_BASE" | \
+		$(CPP) $(CPPFLAGS) -P \
 		-Ichip/$(CHIP) -I$(BDIR) -imacros include/config.h)
-_flash_base=$(shell echo "$$(($(_flash_base_str)))")
+_program_memory_base=$(shell echo "$$(($(_program_memory_base_str)))")
 
 $(eval BOARD_$(UC_BOARD)=y)
 $(eval CHIP_$(UC_CHIP)=y)
diff --git a/Makefile.rules b/Makefile.rules
index 7503884197..17974f4089 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -50,7 +50,7 @@ cmd_raw_to_flat ?= $(out)/util/signer util/signer/rom-testkey.pem $< \
 cmd_elf_to_dis = $(OBJDUMP) -D $< > $@
 cmd_elf_to_hex = $(OBJCOPY) -O ihex $< $@
 cmd_bin_to_hex = $(OBJCOPY) -I binary -O ihex \
-	--change-addresses $(_flash_base) $^ $@
+	--change-addresses $(_program_memory_base) $^ $@
 cmd_smap = $(NM) $< | sort > $@
 cmd_elf = $(CC) $(objs) $(libsharedobjs_elf-y) $(LDFLAGS) \
 	-o $@ -Wl,-T,$< -Wl,-Map,$(patsubst %.elf,%.map,$@)
diff --git a/board/zinger/board.c b/board/zinger/board.c
index 5f1201ea76..f7552523a5 100644
--- a/board/zinger/board.c
+++ b/board/zinger/board.c
@@ -20,8 +20,9 @@
 const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) =
 #include "gen_pub_key.h"
 /* The RSA signature is stored at the end of the RW firmware */
-static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF
-				 + CONFIG_RW_SIZE - RSANUMBYTES;
+static const void *rw_sig = (void *)CONFIG_PROGRAM_MEMORY_BASE +
+				    CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE -
+				    RSANUMBYTES;
 /* Large 768-Byte buffer for RSA computation : could be re-use afterwards... */
 static uint32_t rsa_workbuf[3 * RSANUMWORDS];
 
@@ -29,7 +30,7 @@ extern void pd_rx_handler(void);
 
 /* RW firmware reset vector */
 static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4);
+	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4);
 
 /* External interrupt EXTINT7 for external comparator on PA7 */
 void pd_rx_interrupt(void)
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c
index 31f57da6a3..d6a8d1d4c3 100644
--- a/board/zinger/hardware.c
+++ b/board/zinger/hardware.c
@@ -304,11 +304,11 @@ int adc_disable_watchdog(void)
 
 int flash_physical_write(int offset, int size, const char *data)
 {
-	uint16_t *address = (uint16_t *)(CONFIG_FLASH_BASE + offset);
+	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	int res = EC_SUCCESS;
 	int i;
 
-	if ((uint32_t)address > CONFIG_FLASH_BASE + CONFIG_FLASH_SIZE)
+	if ((uint32_t)address > CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE)
 		return EC_ERROR_INVAL;
 
 	/* unlock CR if needed */
@@ -372,7 +372,7 @@ int flash_physical_erase(int offset, int size)
 	     offset += CONFIG_FLASH_ERASE_SIZE) {
 		int i;
 		/* select page to erase */
-		STM32_FLASH_AR = CONFIG_FLASH_BASE + offset;
+		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= STRT;
 
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
index 9e763d1822..1935378ba5 100644
--- a/chip/g/config_chip.h
+++ b/chip/g/config_chip.h
@@ -23,7 +23,7 @@
 #define CONFIG_RO_HEAD_ROOM	    1024	/* Room for ROM signature. */
 
 /* Describe the flash layout */
-#define CONFIG_FLASH_BASE       0x40000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x40000
 #define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024)
 
 /* Compute the rest of the flash params from these */
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
index 5df44a9315..eaaf46287f 100644
--- a/chip/host/config_chip.h
+++ b/chip/host/config_chip.h
@@ -12,13 +12,13 @@
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
 extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
 
-#define CONFIG_FLASH_BASE       ((uintptr_t)__host_flash)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0010  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080  /* ideal write size */
-#define CONFIG_RAM_BASE         0x0 /* Not supported */
-#define CONFIG_RAM_SIZE         0x0 /* Not supported */
+#define CONFIG_PROGRAM_MEMORY_BASE     ((uintptr_t)__host_flash)
+#define CONFIG_FLASH_BANK_SIZE         0x1000
+#define CONFIG_FLASH_ERASE_SIZE        0x0010  /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE        0x0002  /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE  0x0080  /* ideal write size */
+#define CONFIG_RAM_BASE                0x0 /* Not supported */
+#define CONFIG_RAM_SIZE                0x0 /* Not supported */
 
 #define CONFIG_FPU
 
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 01676a9171..5115e62c24 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -42,7 +42,7 @@
 /* Default task stack size */
 #define TASK_STACK_SIZE             512
 
-#define CONFIG_FLASH_BASE           0x00000000
+#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
 #define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
 #define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index d02e0c530f..65c3f07889 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -52,7 +52,7 @@
 /* Default task stack size */
 #define TASK_STACK_SIZE             512
 
-#define CONFIG_FLASH_BASE           0x00000000
+#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
 #define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
 #define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index f668765482..514f292914 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -99,10 +99,8 @@
 #define CONFIG_FLASH_PHYSICAL_SIZE	0x00040000
 
 /* Program memory base address */
-#define CONFIG_FLASH_BASE		0x00100000
-
+#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
 #define CONFIG_CDRAM_BASE		0x00100000
-#define CONFIG_CDRAM_SIZE		0x00020000
 
 #include "config_flash_layout.h"
 
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index d7a16085c9..4a10175a02 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -16,7 +16,8 @@
 
 /* Non-memmapped, external SPI */
 #define CONFIG_CODERAM_ARCH
-#undef  CONFIG_FLASH_MAPPED
+#define CONFIG_EXTERNAL_STORAGE
+#undef  CONFIG_MAPPED_STORAGE
 #undef  CONFIG_FLASH_PSTATE
 #define CONFIG_SPI_FLASH
 
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index 1e48cb25da..db02a7df57 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -91,7 +91,8 @@ static int spi_flash_readloc(uint8_t *buf_usr,
 
 int spi_image_load(uint32_t offset)
 {
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE);
+	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
+				    CONFIG_PROGRAM_MEMORY_BASE);
 	uint32_t i;
 
 	memset((void *)buf, 0xFF, (CONFIG_FW_IMAGE_SIZE - 4));
@@ -257,7 +258,7 @@ void lfw_main()
 	switch (system_get_image_copy()) {
 	case SYSTEM_IMAGE_RW:
 		uart_puts("lfw-RW load\n");
-		init_addr = CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE;
+		init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
 		spi_image_load(CONFIG_RW_IMAGE_FLASHADDR);
 		break;
 	case SYSTEM_IMAGE_RO:
@@ -267,7 +268,7 @@ void lfw_main()
 	default:
 		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) =
 							SYSTEM_IMAGE_RO;
-		init_addr = CONFIG_RO_MEM_OFF + CONFIG_FLASH_BASE;
+		init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
 	}
 
 	jump_to_image(*(uintptr_t *)(init_addr + 4));
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index ce25c87620..fd8c79a2f1 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -448,7 +448,8 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
 
 uint32_t system_get_lfw_address(void)
 {
-	uint32_t * const lfw_vector = (uint32_t * const) CONFIG_FLASH_BASE;
+	uint32_t * const lfw_vector =
+		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
 
 	return *(lfw_vector + 1);
 }
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 6bb5809235..56db32cc65 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -45,13 +45,13 @@
 
 /*****************************************************************************/
 /* Memory mapping */
-#define CONFIG_RAM_BASE         0x200C0000 /* memory map address of data ram */
-#define CONFIG_RAM_SIZE         (0x00008000 - 0x800) /* 30KB data ram */
-#define CONFIG_CDRAM_BASE       0x100A8000 /* memory map address of code ram */
-#define CONFIG_CDRAM_SIZE       0x00018000 /* 96KB code ram */
-#define CONFIG_FLASH_BASE	0x64000000 /* memory address of spi-flash */
-#define CONFIG_LPRAM_BASE       0x40001600 /* memory address of low power ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
+#define CONFIG_RAM_BASE            0x200C0000 /* memory address of data ram */
+#define CONFIG_RAM_SIZE            (0x00008000 - 0x800) /* 30KB data ram */
+#define CONFIG_CDRAM_BASE          0x100A8000 /* memory address of code ram */
+#define CONFIG_CDRAM_SIZE          0x00018000 /* 96KB code ram */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */
+#define CONFIG_LPRAM_BASE          0x40001600 /* memory address of lpwr ram */
+#define CONFIG_LPRAM_SIZE	   0x00000620 /* 1568B low power ram */
 
 /* System stack size */
 #define CONFIG_STACK_SIZE       4096
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 0988c3ca35..986c0bbfea 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -14,7 +14,10 @@
  */
 
 /* Memmapped, external SPI */
-#define CONFIG_FLASH_MAPPED
+#define CONFIG_EXTERNAL_STORAGE
+#define CONFIG_MAPPED_STORAGE
+/* Storage is memory-mapped, but program runs from SRAM */
+#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
 #undef  CONFIG_FLASH_PSTATE
 
 /* Size of one firmware image in flash */
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/ec_npcxflash.c
index ccaff16872..cc97f69e5a 100644
--- a/chip/npcx/spiflashfw/ec_npcxflash.c
+++ b/chip/npcx/spiflashfw/ec_npcxflash.c
@@ -218,7 +218,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 	uint8_t		*ptr_flash;
 	uint8_t		*ptr_mram;
 
-	ptr_flash = (uint8_t *)(CONFIG_FLASH_BASE + offset);
+	ptr_flash = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	ptr_mram  = (uint8_t *)data;
 	result = 1;
 
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 525049acba..23d66d7882 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -708,7 +708,8 @@ void system_jump_to_booter(void)
 	}
 
 	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset + CONFIG_FLASH_BASE + 4);
+	addr_entry = *(uintptr_t *)(flash_offset +
+				    CONFIG_PROGRAM_MEMORY_BASE + 4);
 
 	download_from_flash(
 		flash_offset,      /* The offset of the data in spi flash */
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
index 328471967c..6f17b59b98 100644
--- a/chip/nrf51/config_chip.h
+++ b/chip/nrf51/config_chip.h
@@ -39,7 +39,7 @@
 #define CONFIG_RAM_SIZE         0x00004000
 
 /* Flash mapping */
-#define CONFIG_FLASH_BASE       0x00000000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index 18c8806908..3cb6e955bd 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00008000
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
index 9b1701a407..e312e61cfd 100644
--- a/chip/stm32/config-stm32f05x.h
+++ b/chip/stm32/config-stm32f05x.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE (64 * 1024)
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index 45b340355c..07e50d8d32 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE (128 * 1024)
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
index fe73db195f..29a0cd248b 100644
--- a/chip/stm32/config-stm32f09x.h
+++ b/chip/stm32/config-stm32f09x.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
 #define CONFIG_FLASH_BANK_SIZE  0x2000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index 42857af2c9..eca9bf58f8 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
 #define CONFIG_FLASH_BANK_SIZE  0x2000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index e751e396cd..2e4f10ad6e 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index dc897253aa..480a0dcbee 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h
index 540855c724..fc6375f20d 100644
--- a/chip/stm32/config-stm32ts60.h
+++ b/chip/stm32/config-stm32ts60.h
@@ -4,7 +4,6 @@
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x0010000 /* Actually 0x8000 */
 #define CONFIG_FLASH_BANK_SIZE  0x1000  /* TODO */
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* TODO erase bank size */
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index be115b5cf9..b2fdecdc2f 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -43,6 +43,8 @@
 #error "Unsupported chip variant"
 #endif
 
+#define CONFIG_PROGRAM_MEMORY_BASE 0x08000000
+
 #include "config_std_internal_flash.h"
 
 /* System stack size */
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
index a1d148a104..c57f072fc2 100644
--- a/chip/stm32/flash-f.c
+++ b/chip/stm32/flash-f.c
@@ -205,7 +205,7 @@ static int write_optb(int byte, uint8_t value)
 
 int flash_physical_write(int offset, int size, const char *data)
 {
-	uint16_t *address = (uint16_t *)(CONFIG_FLASH_BASE + offset);
+	uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	int res = EC_SUCCESS;
 	int i;
 
@@ -285,7 +285,7 @@ int flash_physical_erase(int offset, int size)
 			continue;
 
 		/* select page to erase */
-		STM32_FLASH_AR = CONFIG_FLASH_BASE + offset;
+		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
 
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= STRT;
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
index 5a84d31f46..ce292bb58d 100644
--- a/chip/stm32/flash-stm32l.c
+++ b/chip/stm32/flash-stm32l.c
@@ -161,7 +161,7 @@ void  __attribute__((section(".iram.text")))
 int flash_physical_write(int offset, int size, const char *data)
 {
 	uint32_t *data32 = (uint32_t *)data;
-	uint32_t *address = (uint32_t *)(CONFIG_FLASH_BASE + offset);
+	uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	int res = EC_SUCCESS;
 	int word_mode = 0;
 	int i;
@@ -255,13 +255,14 @@ int flash_physical_erase(int offset, int size)
 	/* Set PROG and ERASE bits */
 	STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE;
 
-	for (address = (uint32_t *)(CONFIG_FLASH_BASE + offset);
+	for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	     size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
 	     address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
 		timestamp_t deadline;
 
 		/* Do nothing if already erased */
-		if (flash_is_erased((uint32_t)address - CONFIG_FLASH_BASE,
+		if (flash_is_erased((uint32_t)address -
+				    CONFIG_PROGRAM_MEMORY_BASE,
 				    CONFIG_FLASH_ERASE_SIZE))
 			continue;
 
diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S
index d956a3471d..546ad26c63 100644
--- a/common/firmware_image.lds.S
+++ b/common/firmware_image.lds.S
@@ -9,7 +9,7 @@ OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
 OUTPUT_ARCH(BFD_ARCH)
 MEMORY
 {
-    FLASH (rx) : ORIGIN = CONFIG_FLASH_BASE, LENGTH = CONFIG_FLASH_SIZE
+    FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE, LENGTH = CONFIG_FLASH_SIZE
 }
 SECTIONS
 {
@@ -17,15 +17,16 @@ SECTIONS
 #if defined(NPCX_RO_HEADER)
 /* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
  * or some struture which doesn't belong to FW */
-    .image.RO : AT(CONFIG_FLASH_BASE + CONFIG_RO_STORAGE_OFF) {
+    .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_STORAGE_OFF) {
 #else
-    .image.RO : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF) {
+    .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) {
 #endif
         *(.image.RO)
     } > FLASH =0xff
     . = ALIGN(CONFIG_FLASH_BANK_SIZE);
 #ifdef CONFIG_SHAREDLIB
-    .image.libsharedobjs : AT(CONFIG_FLASH_BASE + CONFIG_SHAREDLIB_MEM_OFF) {
+    .image.libsharedobjs : AT(CONFIG_PROGRAM_MEMORY_BASE + \
+                              CONFIG_SHAREDLIB_MEM_OFF) {
         *(.image.libsharedobjs)
     } > FLASH =0xff
     . = ALIGN(CONFIG_FLASH_BANK_SIZE);
@@ -34,13 +35,14 @@ SECTIONS
 /* This is applicable to ECs in which RO and RW execution is
 mapped to the same location but we still have to generate an ec.bin with RO
 and RW images at different Flash offset */
-    .image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) {
+    .image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF + \
+                   CONFIG_RO_SIZE) {
 #else
-    .image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF) {
+    .image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF) {
 #endif
         *(.image.RW)
     } > FLASH =0xff
-    .padding : AT(CONFIG_FLASH_BASE + CONFIG_FLASH_SIZE - 1) {
+    .padding : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE - 1) {
         BYTE(0xff);
     } > FLASH =0xff
 }
diff --git a/common/flash.c b/common/flash.c
index b5dad96438..0f45b8e4d5 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -29,8 +29,8 @@
  * If flash isn't mapped to the EC's address space, it's probably SPI, and
  * should be using SPI write protect, not PSTATE.
  */
-#ifndef CONFIG_FLASH_MAPPED
-#error "PSTATE should only be used with internal mapped mapped flash."
+#if !defined(CONFIG_INTERNAL_STORAGE) || !defined(CONFIG_MAPPED_STORAGE)
+#error "PSTATE should only be used with internal mem-mapped flash."
 #endif
 
 #ifdef CONFIG_FLASH_PSTATE_BANK
@@ -101,7 +101,7 @@ int flash_range_ok(int offset, int size_req, int align)
 	return 1;
 }
 
-#ifdef CONFIG_FLASH_MAPPED
+#ifdef CONFIG_MAPPED_STORAGE
 /**
  * Get the physical memory address of a flash offset
  *
@@ -115,7 +115,7 @@ int flash_range_ok(int offset, int size_req, int align)
  */
 static const char *flash_physical_dataptr(int offset)
 {
-	return (char *)((uintptr_t)CONFIG_FLASH_BASE + offset);
+	return (char *)((uintptr_t)CONFIG_PROGRAM_MEMORY_BASE + offset);
 }
 
 int flash_dataptr(int offset, int size_req, int align, const char **ptrp)
@@ -246,7 +246,8 @@ static int flash_write_pstate(uint32_t flags)
 	 * Write a new pstate.  We can overwrite the existing value, because
 	 * we're only moving bits from the erased state to the unerased state.
 	 */
-	return flash_physical_write(get_pstate_addr() - CONFIG_FLASH_BASE,
+	return flash_physical_write(get_pstate_addr() -
+				    CONFIG_PROGRAM_MEMORY_BASE,
 				    sizeof(new_pstate),
 				    (const char *)&new_pstate);
 }
@@ -258,7 +259,7 @@ int flash_is_erased(uint32_t offset, int size)
 {
 	const uint32_t *ptr;
 
-#ifdef CONFIG_FLASH_MAPPED
+#ifdef CONFIG_MAPPED_STORAGE
 	/* Use pointer directly to flash */
 	if (flash_dataptr(offset, size, sizeof(uint32_t),
 			  (const char **)&ptr) < 0)
@@ -294,7 +295,7 @@ int flash_is_erased(uint32_t offset, int size)
 
 int flash_read(int offset, int size, char *data)
 {
-#ifdef CONFIG_FLASH_MAPPED
+#ifdef CONFIG_MAPPED_STORAGE
 	const char *src;
 
 	if (flash_dataptr(offset, size, 1, &src) < 0)
diff --git a/common/fmap.c b/common/fmap.c
index e61df8d968..28800ee663 100644
--- a/common/fmap.c
+++ b/common/fmap.c
@@ -17,14 +17,15 @@
 #define FMAP_VER_MINOR 0
 
 /*
- * For address containing CONFIG_FLASH_BASE (symbols in *.RO.lds.S and
+ * For address containing CONFIG_PROGRAM_MEMORY_BASE (symbols in *.RO.lds.S and
  * variable), this computes the offset to the start of the image on flash.
  */
 
 #ifdef NPCX_RO_HEADER
 #define RELATIVE_RO(addr) ((addr) - CONFIG_CDRAM_BASE)
 #else
-#define RELATIVE_RO(addr) ((addr) - CONFIG_FLASH_BASE - CONFIG_RO_MEM_OFF)
+#define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \
+			   CONFIG_RO_MEM_OFF)
 #endif
 
 struct fmap_header {
@@ -59,7 +60,7 @@ const struct _ec_fmap {
 		.fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'},
 		.fmap_ver_major = FMAP_VER_MAJOR,
 		.fmap_ver_minor = FMAP_VER_MINOR,
-		.fmap_base = CONFIG_FLASH_BASE,
+		.fmap_base = CONFIG_PROGRAM_MEMORY_BASE,
 		.fmap_size = CONFIG_FLASH_SIZE,
 		.fmap_name = "EC_FMAP",
 		.fmap_nareas = NUM_EC_FMAP_AREAS,
diff --git a/common/rwsig.c b/common/rwsig.c
index ef86c19c23..c58e7ab84d 100644
--- a/common/rwsig.c
+++ b/common/rwsig.c
@@ -25,12 +25,13 @@ const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) =
 #include "gen_pub_key.h"
 
 /* The RSA signature is stored at the end of the RW firmware */
-static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF
+static const void *rw_sig = (void *)CONFIG_PROGRAM_MEMORY_BASE
+				 + CONFIG_RW_MEM_OFF
 				 + CONFIG_RW_SIZE - RSANUMBYTES;
 
 /* RW firmware reset vector */
 static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4);
+	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
 
 void check_rw_signature(void)
 {
@@ -59,7 +60,8 @@ void check_rw_signature(void)
 	/* SHA-256 Hash of the RW firmware */
 	/* TODO(crosbug.com/p/44803): Do we have to hash the whole region? */
 	SHA256_init(&ctx);
-	SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF,
+	SHA256_update(&ctx, (void *)CONFIG_PROGRAM_MEMORY_BASE
+		      + CONFIG_RW_MEM_OFF,
 		      CONFIG_RW_SIZE - RSANUMBYTES);
 	hash = SHA256_final(&ctx);
 
diff --git a/common/system.c b/common/system.c
index 42eb91bf71..d617aa39f1 100644
--- a/common/system.c
+++ b/common/system.c
@@ -100,15 +100,11 @@ uint32_t sleep_mask;
  */
 static uintptr_t get_program_memory_addr(enum system_image_copy_t copy)
 {
-	/*
-	 * TODO(crosbug.com/p/23796): CONFIG_FLASH_BASE has overloaded meaning,
-	 * add an explicit CONFIG for program memory base for all boards.
-	 */
 	switch (copy) {
 	case SYSTEM_IMAGE_RO:
-		return CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF;
+		return CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF;
 	case SYSTEM_IMAGE_RW:
-		return CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF;
+		return CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF;
 	default:
 		return 0xffffffff;
 	}
@@ -323,7 +319,7 @@ test_mockable enum system_image_copy_t system_get_image_copy(void)
 	return system_get_shrspi_image_copy();
 #else
 	uintptr_t my_addr = (uintptr_t)system_get_image_copy -
-			    CONFIG_FLASH_BASE;
+			    CONFIG_PROGRAM_MEMORY_BASE;
 
 	if (my_addr >= CONFIG_RO_MEM_OFF &&
 	    my_addr < (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE))
@@ -339,7 +335,7 @@ test_mockable enum system_image_copy_t system_get_image_copy(void)
 
 int system_get_image_used(enum system_image_copy_t copy)
 {
-#if !defined(CONFIG_FLASH_MAPPED) && defined(CONFIG_CODERAM_ARCH)
+#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
 	int image_offset;
 	uint8_t buf[SPI_FLASH_MAX_WRITE_SIZE];
 #endif
@@ -354,7 +350,7 @@ int system_get_image_used(enum system_image_copy_t copy)
 	 * last byte of the image.  See ec.lds.S for how this is inserted at
 	 * the end of the image.
 	 */
-#if !defined(CONFIG_FLASH_MAPPED) && defined(CONFIG_CODERAM_ARCH)
+#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
 	image_offset = (copy == SYSTEM_IMAGE_RW) ? CONFIG_RW_STORAGE_OFF :
 			CONFIG_RO_STORAGE_OFF;
 	image = buf;
@@ -542,7 +538,7 @@ int system_run_image_copy(enum system_image_copy_t copy)
 
 const char *system_get_version(enum system_image_copy_t copy)
 {
-#if !defined(CONFIG_FLASH_MAPPED) && defined(CONFIG_CODERAM_ARCH)
+#if !defined(CONFIG_MAPPED_STORAGE) && defined(CONFIG_CODERAM_ARCH)
 	static struct version_struct vdata;
 #endif
 
@@ -564,7 +560,7 @@ const char *system_get_version(enum system_image_copy_t copy)
 	addr = ((uintptr_t)&version_data -
 	       get_program_memory_addr(active_copy));
 #ifdef CONFIG_CODERAM_ARCH
-#ifdef CONFIG_FLASH_MAPPED
+#ifdef CONFIG_MAPPED_STORAGE
 	/* Geometry constants have non-standard meaning for npcx */
 	addr = ((uintptr_t)&version_data - CONFIG_CDRAM_BASE +
 			   get_program_memory_addr(copy));
@@ -576,7 +572,7 @@ const char *system_get_version(enum system_image_copy_t copy)
 	 */
 	addr += (copy == SYSTEM_IMAGE_RW) ? CONFIG_RW_STORAGE_OFF :
 					    CONFIG_RO_STORAGE_OFF;
-#endif /* CONFIG_FLASH_MAPPED */
+#endif /* CONFIG_MAPPED_STORAGE */
 #else /* CONFIG_CODERAM_ARCH */
 	/*
 	 * Read version from program memory, which is always populated with
@@ -585,7 +581,7 @@ const char *system_get_version(enum system_image_copy_t copy)
 	addr += get_program_memory_addr(copy);
 #endif /*CONFIG_CODERAM_ARCH */
 
-#if defined(CONFIG_FLASH_MAPPED) || !defined(CONFIG_CODERAM_ARCH)
+#if defined(CONFIG_MAPPED_STORAGE) || !defined(CONFIG_CODERAM_ARCH)
 	/* Directly access the data from program memory or mapped flash. */
 	v = (const struct version_struct *)addr;
 #else
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
index 91bbdb15e4..e628e6e556 100644
--- a/common/usb_pd_policy.c
+++ b/common/usb_pd_policy.c
@@ -826,7 +826,7 @@ uint8_t *flash_hash_rw(void)
 	if (rw_flash_changed) {
 		rw_flash_changed = 0;
 		SHA256_init(&ctx);
-		SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE +
+		SHA256_update(&ctx, (void *)CONFIG_PROGRAM_MEMORY_BASE +
 			      CONFIG_RW_MEM_OFF,
 			      CONFIG_RW_SIZE - RSANUMBYTES);
 		return SHA256_final(&ctx);
diff --git a/common/vboot_hash.c b/common/vboot_hash.c
index ff2c56fb59..7726ef7043 100644
--- a/common/vboot_hash.c
+++ b/common/vboot_hash.c
@@ -63,7 +63,7 @@ void vboot_hash_abort(void)
 	}
 }
 
-#ifndef CONFIG_FLASH_MAPPED
+#ifndef CONFIG_MAPPED_STORAGE
 
 static void vboot_hash_next_chunk(void);
 
@@ -111,8 +111,8 @@ static void vboot_hash_next_chunk(void)
 	/* Compute the next chunk of hash */
 	size = MIN(CHUNK_SIZE, data_size - curr_pos);
 
-#ifdef CONFIG_FLASH_MAPPED
-	SHA256_update(&ctx, (const uint8_t *)(CONFIG_FLASH_BASE +
+#ifdef CONFIG_MAPPED_STORAGE
+	SHA256_update(&ctx, (const uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE +
 					      data_offset + curr_pos), size);
 #else
 	if (read_and_hash_chunk(data_offset + curr_pos, size) != EC_SUCCESS)
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index 11c91ba301..6e5eefba32 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -7,7 +7,7 @@
 
 #define FW_MEM_OFF_(section) CONFIG_##section##_MEM_OFF
 #define FW_MEM_OFF(section) (FW_MEM_OFF_(section))
-#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_MEM_OFF(section))
+#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(section))
 
 #define FW_SIZE_(section) CONFIG_##section##_SIZE
 #define FW_SIZE(section) FW_SIZE_(section)
@@ -32,16 +32,16 @@ MEMORY
     FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
     IRAM (rw)  : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
 #ifdef CONFIG_CODERAM_ARCH
-#ifdef CONFIG_FLASH_MAPPED
+#ifdef CONFIG_MAPPED_STORAGE
    /* Geometry constants have non-standard meaning for npcx */
    CDRAM (rx) : \
         ORIGIN = CONFIG_CDRAM_BASE, \
         LENGTH = CONFIG_CDRAM_SIZE
-#else /* CONFIG_FLASH_MAPPED */
+#else /* CONFIG_MAPPED_STORAGE */
    CDRAM (rx) : \
         ORIGIN = CONFIG_CDRAM_BASE + FW_MEM_OFF(SECTION), \
         LENGTH = FW_SIZE(SECTION)
-#endif /* CONFIG_FLASH_MAPPED */
+#endif /* CONFIG_MAPPED_STORAGE */
 #endif /* CONFIG_CODERAM_ARCH */
 #ifdef RSA_PUBLIC_KEY_SIZE
     PSTATE(r)  : \
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index 8f3f382c98..629046ed0b 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -6,7 +6,7 @@
 #include "rsa.h"
 
 #define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section))
+#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
 
 #define FW_SIZE_(section) CONFIG_##section##_SIZE
 #define FW_SIZE(section) FW_SIZE_(section)
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
index d3e8cc7c20..13f090ee28 100644
--- a/core/nds32/ec.lds.S
+++ b/core/nds32/ec.lds.S
@@ -5,7 +5,7 @@
 #include "config.h"
 
 #define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section))
+#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
 
 #define FW_SIZE_(section) CONFIG_##section##_SIZE
 #define FW_SIZE(section) FW_SIZE_(section)
diff --git a/include/config.h b/include/config.h
index c14af4bf7d..248c7c4813 100644
--- a/include/config.h
+++ b/include/config.h
@@ -689,15 +689,30 @@
 #define CONFIG_FLASH
 
 #undef CONFIG_FLASH_BANK_SIZE
-#undef CONFIG_FLASH_BASE
 #undef CONFIG_FLASH_ERASED_VALUE32
 #undef CONFIG_FLASH_ERASE_SIZE
 
+/* Base address of program memory */
+#undef CONFIG_PROGRAM_MEMORY_BASE
+
+/*
+ * EC code can reside on internal or external storage. Only one of these
+ * CONFIGs should be defined.
+ */
+#undef CONFIG_EXTERNAL_STORAGE
+#undef CONFIG_INTERNAL_STORAGE
+
 /*
  * Flash is directly mapped into the EC's address space.  If this is not
  * defined, the flash driver must implement flash_physical_read().
  */
-#define CONFIG_FLASH_MAPPED
+#define CONFIG_MAPPED_STORAGE
+
+/*
+ * Base address of memory-mapped flash storage, for platforms which define
+ * CONFIG_MAPPED_STORAGE.
+ */
+#undef CONFIG_MAPPED_STORAGE_BASE
 
 #undef CONFIG_FLASH_PHYSICAL_SIZE
 #undef CONFIG_FLASH_PROTECT_NEXT_BOOT
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
index 10cd5baf5c..51bd011304 100644
--- a/include/config_std_internal_flash.h
+++ b/include/config_std_internal_flash.h
@@ -33,9 +33,13 @@
  */
 
 /* Memory-mapped internal flash w/ PSTATE */
-#define CONFIG_FLASH_MAPPED
+#define CONFIG_INTERNAL_STORAGE
+#define CONFIG_MAPPED_STORAGE
 #define CONFIG_FLASH_PSTATE
 
+/* Program is run directly from storage */
+#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
+
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
  * register with persistent state.
diff --git a/include/flash.h b/include/flash.h
index 0c3d12e1e1..24922e04dc 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -201,7 +201,7 @@ int flash_dataptr(int offset, int size_req, int align, const char **ptrp);
 /**
  * Read from flash.
  *
- * If flash is mapped (CONFIG_FLASH_MAPPED), it is usually more efficient to
+ * If flash is mapped (CONFIG_MAPPED_STORAGE), it is usually more efficient to
  * use flash_dataptr() to get a pointer directly to the flash memory rather
  * than use flash_read(), since the former saves a memcpy() operation.
  *
diff --git a/test/flash.c b/test/flash.c
index 3f7676d0f1..da3df8a1ad 100644
--- a/test/flash.c
+++ b/test/flash.c
@@ -255,7 +255,8 @@ static int test_read(void)
 	TEST_ASSERT(!flash_is_erased(0, sizeof(buf)));
 
 	TEST_ASSERT(host_command_read(0, sizeof(buf), buf) == EC_RES_SUCCESS);
-	TEST_ASSERT_ARRAY_EQ(buf, (char *)CONFIG_FLASH_BASE, sizeof(buf));
+	TEST_ASSERT_ARRAY_EQ(buf, (char *)CONFIG_PROGRAM_MEMORY_BASE,
+			     sizeof(buf));
 
 	return EC_SUCCESS;
 }
author	Shawn Nematbakhsh <shawnn@chromium.org>	2015-09-04 19:09:33 -0700
committer	chrome-bot <chrome-bot@chromium.org>	2015-09-16 14:49:31 -0700
commit	d58e54730c03290296df5bb65cb84264e4b2facc (patch)
tree	d736570c84a0e9737b8881ec68b073327a5c2ae5
parent	4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff)
download	chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz