diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-01-22 14:53:14 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-03 16:42:03 +0000 |
| commit | fb482f6e05a32ddfa12c72436151a25142ea409c (patch) | |
| tree | 1696923ae882e547cae45f613f0792ef73531978 | |
| parent | 67d7d755568a3a7584022bc8a7f1ccc0655e02cf (diff) | |
| download | chrome-ec-fb482f6e05a32ddfa12c72436151a25142ea409c.tar.gz | |
guybrush: Enable hibernate_psl and low_power_idle
Enable CONFIG_HIBERNATE_PSL and CONFIG_LOW_POWER_IDLE.
Reorginize power configs.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: If2c1de703c72d660a1ad61a4270c735161dd6abe
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2645080
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
| -rw-r--r-- | baseboard/guybrush/baseboard.h | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h index adbf1d1228..463834f310 100644 --- a/baseboard/guybrush/baseboard.h +++ b/baseboard/guybrush/baseboard.h @@ -23,27 +23,29 @@ #undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO -#define CONFIG_POWER_COMMON -#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 +#define CONFIG_HIBERNATE_PSL +#define CONFIG_LOW_POWER_IDLE #define CONFIG_POWER_BUTTON -#define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 #define G3_TO_PWRBTN_DELAY_MS 80 -#define SAFE_RESET_VBUS_MV 5000 -#define SAFE_RESET_VBUS_DELAY_MS 900 #define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_EN_PWR_A GPIO_EN_PWR_Z1 #define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L #define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L -#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L #define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L #define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD +#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL #define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD #define GPIO_S5_PGOOD GPIO_PG_PWR_S5 -#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD #define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_EN_PWR_A GPIO_EN_PWR_Z1 +#define SAFE_RESET_VBUS_DELAY_MS 900 +#define SAFE_RESET_VBUS_MV 5000 /* * On power-on, H1 releases the EC from reset but then quickly asserts and * releases the reset a second time. This means the EC sees 2 resets: @@ -58,6 +60,7 @@ #define CONFIG_THROTTLE_AP #define CONFIG_TEMP_SENSOR_SB_TSI #define CONFIG_THERMISTOR +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW #define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL /* Flash Config */ @@ -66,6 +69,7 @@ #define GPIO_WP_L GPIO_EC_WP_L /* Host communication */ +#define CONFIG_CMD_CHARGEN #define CONFIG_HOSTCMD_ESPI #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT |