diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2018-01-16 09:40:00 +0100 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-17 06:20:38 -0800 |
commit | c10a631026fb02b356435f4f7d150495b2cec223 (patch) | |
tree | 6cd6573ab9d1caaf3a024f2299df5f0f2dafb4cd | |
parent | 9d38e4664150579503f70b03b35e1dd1bedb7920 (diff) | |
download | chrome-ec-c10a631026fb02b356435f4f7d150495b2cec223.tar.gz |
meowth_fp: add flashing script
Simple shell to flash the FP MCU firmware from the AP through the STM32
DFU mode (over the SPI interface).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991, b:36125319
TEST=run flash_fp_mcu on Meowth and see a new FP MCU is flashed
Change-Id: I99af754b3ed4916ee04a800859f1b28feb640de1
Reviewed-on: https://chromium-review.googlesource.com/866840
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rwxr-xr-x | board/meowth_fp/flash_fp_mcu | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/board/meowth_fp/flash_fp_mcu b/board/meowth_fp/flash_fp_mcu new file mode 100755 index 0000000000..41ffbb9ab0 --- /dev/null +++ b/board/meowth_fp/flash_fp_mcu @@ -0,0 +1,72 @@ +#!/bin/sh +# Copyright 2018 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Meowth configuration +SPIDEV="/dev/spidev1.0" +# Cannonlake PCH GPIOs +GPIOCHIP="gpiochip268" +# GSPI1 ACPI device for FP MCU +SPIID="spi-PRP0001:00" +# FPMCU RST_ODL is on GPP_A23 = 268 + 23 = 291 +GPIO_NRST=291 +# FPMCU BOOT0 is on GPP_A21 = 268 + 21 = 289 +GPIO_BOOT0=289 + +if [ ! -e "/sys/class/gpio/${GPIOCHIP}" ] +then + echo "Cannot find the GPIO chip. Are your running on Meowth ?" + exit 1 +fi + +if [ ! -f "$1" ] +then + echo "Invalid image file: $1" + echo "Usage: $0 ec.bin" + exit 1 +fi + +# Remove cros_fp if present +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/unbind + +# Configure the MCU Boot0 and NRST GPIOs +echo ${GPIO_BOOT0} > /sys/class/gpio/export +echo "out" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction +echo ${GPIO_NRST} > /sys/class/gpio/export +echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction + +# Reset sequence to enter bootloader mode +echo 1 > /sys/class/gpio/gpio${GPIO_BOOT0}/value +echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value +echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value + +echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction + +# load spidev (fail on cros-ec-spi first to change modalias) +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind +echo "${SPIID}" > /sys/bus/spi/drivers/spidev/bind + +stm32mon -s ${SPIDEV} -e -w $1 + +# unload spidev +echo "${SPIID}" > /sys/bus/spi/drivers/spidev/unbind + +# Go back to normal mode +echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction +echo 0 > /sys/class/gpio/gpio${GPIO_BOOT0}/value +echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value +echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value + +# Give up GPIO control +echo "in" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction +echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction +echo ${GPIO_BOOT0} > /sys/class/gpio/unexport +echo ${GPIO_NRST} > /sys/class/gpio/unexport + +# wait for FP MCU to come back up +sleep 1 +# Put back cros_fp driver +echo "${SPIID}" > /sys/bus/spi/drivers/cros-ec-spi/bind +# Test it +ectool --name=cros_fp version |