diff options
| author | Divya Sasidharan <divya.s.sasidharan@intel.com> | 2018-04-09 09:59:14 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-04-10 19:13:31 -0700 |
| commit | dccaf9d9fce04a1e2fd1eb51fb85627ef2976146 (patch) | |
| tree | 8fdb4d46a74ddfce01d648a723d73468bc374453 | |
| parent | 3a96c3cec4754abf953709b4f19c03a062c4d04a (diff) | |
| download | chrome-ec-dccaf9d9fce04a1e2fd1eb51fb85627ef2976146.tar.gz | |
yorp: Enable DP alternate mode
This code enables alternate mode path for
DP for both TypeC ports.
BUG=b:77496487
BRANCH=None
TEST=On yorp; check if the mux is set correctly
for DP use cases. When PD message for hot plug is received
by EC, EC (write register) ---> TCPC (GPIO) ---> SoC,
and display comes up with both ports.
Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1003330
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | board/yorp/gpio.inc | 4 | ||||
| -rw-r--r-- | board/yorp/usb_pd_policy.c | 28 |
2 files changed, 26 insertions, 6 deletions
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index 4b202228a2..ab28e42d5d 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -92,14 +92,14 @@ GPIO(USB_A_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH) /* Enable A0/A1 1.5A Charging /* USB_C0_PD_RST_L isn't connected to PIN(6,2) since ANX TCPC doesn't have reset */ GPIO(USB_C0_BC12_VBUS_ON, PIN(6, 3), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT) /* C0 BC1.2 Detect */ -GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_ODR_HIGH | /* C0 DP Hotplug Detect */ +GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT | /* C0 DP Hotplug Detect */ GPIO_SEL_1P8V) GPIO(USB_C1_PD_RST_ODL, PIN(7, 0), GPIO_ODR_HIGH) /* C1 PD Reset */ GPIO(EN_USB_C1_5V_OUT, PIN(0, 3), GPIO_OUT_LOW) /* C1 Source 5V */ GPIO(USB_C1_CHARGE_ON, PIN(4, 0), GPIO_OUT_LOW) /* C1 Accept input voltage*/ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ -GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_ODR_HIGH | /* C1 DP Hotplug Detect */ +GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) /* LED */ diff --git a/board/yorp/usb_pd_policy.c b/board/yorp/usb_pd_policy.c index 0d7db82725..582381615b 100644 --- a/board/yorp/usb_pd_policy.c +++ b/board/yorp/usb_pd_policy.c @@ -312,18 +312,38 @@ static int svdm_dp_config(int port, uint32_t *payload) static void svdm_dp_post_config(int port) { - /* TODO(b/74127309): Flesh out USB code */ + const struct usb_mux *mux = &usb_muxes[port]; + + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; + mux->hpd_update(port, 1, 0); } static int svdm_dp_attention(int port, uint32_t *payload) { - /* TODO(b/74127309): Flesh out USB code */ - return 1; /* ack */ + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + const struct usb_mux *mux = &usb_muxes[port]; + + dp_status[port] = payload[1]; + if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { + if (lvl) + dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; + return 1; + } + mux->hpd_update(port, lvl, irq); + + /* ack */ + return 1; } static void svdm_exit_dp_mode(int port) { - /* TODO(b/74127309): Flesh out USB code */ + const struct usb_mux *mux = &usb_muxes[port]; + + svdm_safe_dp_mode(port); + mux->hpd_update(port, 0, 0); } static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) |