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| author | Divya Sasidharan <divya.s.sasidharan@intel.com> | 2018-04-11 13:47:59 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-04-11 22:52:42 -0700 |
| commit | 36df8427f457c38a4fd435c6d05336a0460a681f (patch) | |
| tree | 83fbb5610dfd9a585a20bc1cbd1a094e5ef3f814 | |
| parent | a696908bf39b1f14e158b06d81de7b442b26a525 (diff) | |
| download | chrome-ec-36df8427f457c38a4fd435c6d05336a0460a681f.tar.gz | |
yorp: Configure CONFIG_EXTPOWER_DEBOUNCE_MS
Without this configuration defined the board assumes
battery only mode for G3->S5 boot up power sequence and
thereby waits for power button press.
BUG=b:76230069;b:75974377
BRANCH=None
TEST=On yorp, with battery and external power connected
reboot on EC console boot the SoC to S0. Verify on both ports.
Change-Id: I837b7f99bd3c238ce74e394c773169d703ad9392
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1008247
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | board/yorp/board.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/board/yorp/board.h b/board/yorp/board.h index bf3522cd45..e827677578 100644 --- a/board/yorp/board.h +++ b/board/yorp/board.h @@ -143,7 +143,12 @@ #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_EXTPOWER_GPIO -/* TODO(b/75974377), increase CONFIG_EXTPOWER_DEBOUNCE_MS from 30 to 1000? */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +/* + * ISL923x driver sets "Adapter insertion to Switching Debounce" + * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms + */ +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #ifndef __ASSEMBLER__ |