diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-05-23 09:54:32 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-05-23 20:35:15 -0700 |
| commit | 0d47794e6c511a896a1b544e222e792d1e1bbfcc (patch) | |
| tree | 2d54238659bd76c0c75f2591f3d1402dc33c825f | |
| parent | 57ed31bcc5af3d79a24dfc1937560c922685d280 (diff) | |
| download | chrome-ec-0d47794e6c511a896a1b544e222e792d1e1bbfcc.tar.gz | |
chip/it83xx: Configure IRQTP for KBC when using eSPI
SERIIRQ# is by default deasserted level high. However, when using
eSPI, SERIRQ# is routed over virtual wire as interrupt event. As per
eSPI base spec (doc#327432), all virtual wire interrupt events are
deasserted level low. Thus, it is necessary to configure this
interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
signal appropriately over eSPI/LPC depending upon the selected mode.
BUG=b:79897267
BRANCH=None
TEST=Verified using evtest that keypresses are properly identified on
the OS side.
Change-Id: Ie3b92f20fa915ba8f17dcbcb600ebfe5cbfb4d57
Signed-off-by: Dino Li <dino.li@ite.corp-partner.google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069570
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | chip/it83xx/ec2i.c | 22 | ||||
| -rw-r--r-- | chip/it83xx/ec2i_chip.h | 3 |
2 files changed, 25 insertions, 0 deletions
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c index 31ed7b4595..5807b3ed32 100644 --- a/chip/it83xx/ec2i.c +++ b/chip/it83xx/ec2i.c @@ -19,6 +19,28 @@ static const struct ec2i_t pnpcfg_settings[] = { {HOST_INDEX_LDN, LDN_KBC_KEYBOARD}, /* Set IRQ=01h for logical device */ {HOST_INDEX_IRQNUMX, 0x01}, + /* Configure IRQTP for KBC. */ +#ifdef CONFIG_HOSTCMD_ESPI + /* + * Interrupt request type select (IRQTP) for KBC. + * bit 1, 0: IRQ request is buffered and applied to SERIRQ + * 1: IRQ request is inverted before being applied to SERIRQ + * bit 0, 0: Edge triggered mode + * 1: Level triggered mode + * + * SERIRQ# is by default deasserted level high. However, when using + * eSPI, SERIRQ# is routed over virtual wire as interrupt event. As + * per eSPI base spec (doc#327432), all virtual wire interrupt events + * are deasserted level low. Thus, it is necessary to configure this + * interrupt as inverted. ITE hardware takes care of routing the SERIRQ# + * signal appropriately over eSPI / LPC depending upon the selected + * mode. + * + * Additionally, this interrupt is configured as edge-triggered on the + * host side. So, match the trigger mode on the EC side as well. + */ + {HOST_INDEX_IRQTP, 0x02}, +#endif /* Enable logical device */ {HOST_INDEX_LDA, 0x01}, diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h index 8802e3d0b8..9510f75efc 100644 --- a/chip/it83xx/ec2i_chip.h +++ b/chip/it83xx/ec2i_chip.h @@ -16,6 +16,9 @@ enum ec2i_setting { EC2I_SET_KB_LDN, EC2I_SET_KB_IRQ, +#ifdef CONFIG_HOSTCMD_ESPI + EC2I_SET_KB_IRQ_TYPE, +#endif EC2I_SET_KB_ENABLE, EC2I_SET_MOUSE_LDN, EC2I_SET_MOUSE_IRQ, |