diff options
| author | Jonathan Brandmeyer <jbrandmeyer@chromium.org> | 2018-07-18 11:29:55 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-19 12:14:04 -0700 |
| commit | 93008703b1d8ebd92ac65e97c0c0411d02d1add0 (patch) | |
| tree | 8d326056c5a7c5fb169d09389aa6ddda0ee62dba | |
| parent | 506fe0d5ed02326db5620007ec1870cfab800a81 (diff) | |
| download | chrome-ec-93008703b1d8ebd92ac65e97c0c0411d02d1add0.tar.gz | |
careena: Correct GPIO_SYS_RESET_L pin definition.
Caveat: Careena early generation hardware was reworked to a state which
does not map SYS_RESET_L to any pin on the EC. This change updates the
config to the next hardware gen.
TEST=make -j buildall, schematic review
BRANCH=none
BUG=b:111593365, b:109874594
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Change-Id: Icb1ca7ccbacd98f960e4f44041281d1b2ca94e6e
Reviewed-on: https://chromium-review.googlesource.com/1142236
Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | board/careena/gpio.inc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc index 344d2d6774..76ba691e0c 100644 --- a/board/careena/gpio.inc +++ b/board/careena/gpio.inc @@ -31,12 +31,11 @@ GPIO(ENABLE_BACKLIGHT_L, PIN(D, 3), GPIO_OUT_HIGH) /* Enable Backlight */ GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power Button to SOC */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_OUT_HIGH) /* Wake SOC */ -GPIO(SYS_RESET_L, PIN(3, 5), GPIO_ODR_HIGH) /* Cold Reset to SOC */ +GPIO(SYS_RESET_L, PIN(E, 4), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) /* Case Closed Debug Mode */ GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC Entering RW */ GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP) /* Battery Present */ GPIO(PCH_SYS_PWROK, PIN(D, 6), GPIO_OUT_LOW) /* Power OK to SOC */ -GPIO(EC_APU_RST, PIN(E, 4), GPIO_INPUT) /* Reset to SOC */ GPIO(CPU_PROCHOT, PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* PROCHOT to SOC */ GPIO(APU_ALERT_L, PIN(A, 2), GPIO_INPUT) /* Alert to SOC */ GPIO(3AXIS_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* 3 Axis Accel */ |