diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-07-17 09:20:06 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-18 18:15:24 -0700 |
| commit | d22bdeeaecd864835eacb9c22e05f09050fb0237 (patch) | |
| tree | fa8162a8029f161f1eb4d0facfcf838ab8213f3b | |
| parent | 9ba60c726b979cdddd31d1a30f48c85441dc9070 (diff) | |
| download | chrome-ec-d22bdeeaecd864835eacb9c22e05f09050fb0237.tar.gz | |
phaser: Change USB2_OTG_ID to open drain
USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE
and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on
USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be
open drain so that it is actively driven from the EC when it wants to
pull it low. Otherwise, the pin would be tri-stated from the EC side
allowing it to be pulled up to 1.8V because of the SoC internal pull-up.
BUG=b:111102089
BRANCH=None
TEST=Verified that there is no more leakage of 1.8V rail.
Change-Id: I306e809f6b3ad31596f7f11da68311afcd1eac32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1140498
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | board/phaser/gpio.inc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index aba6bdf429..73ba0f728d 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -128,7 +128,12 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */ GPIO_SEL_1P8V) -GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_OUT_LOW) /* OTG ID */ +/* + * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it + * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it + * high. + */ +GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_ODR_LOW) /* OTG ID */ /* LED */ GPIO(BAT_LED_ORANGE_L, PIN(C, 3), GPIO_OUT_HIGH) /* LED_1_L */ |