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authorFurquan Shaikh <furquan@google.com>2018-07-17 09:31:33 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-07-18 21:59:00 -0700
commitabb18f20cdbff403794ef3e2b0087ff6a4aa504a (patch)
tree44691bdb1438f460f06ef905dd4da071cfcb4480
parent40787b695522e837a8c63a90e02e654dcb6adbd8 (diff)
downloadchrome-ec-abb18f20cdbff403794ef3e2b0087ff6a4aa504a.tar.gz
fleex: Change USB2_OTG_ID to open drain
USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be open drain so that it is actively driven from the EC when it wants to pull it low. Otherwise, the pin would be tri-stated from the EC side allowing it to be pulled up to 1.8V because of the SoC internal pull-up. BUG=None BRANCH=None TEST=None Change-Id: Icfe9f4ca6982d70f0e42bee589b68b7c4b768d9f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140501 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
-rw-r--r--board/fleex/gpio.inc8
1 files changed, 7 insertions, 1 deletions
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
index ccba4cb909..2457854314 100644
--- a/board/fleex/gpio.inc
+++ b/board/fleex/gpio.inc
@@ -106,7 +106,13 @@ GPIO(USB_C1_BC12_VBUS_ON, PIN(B, 1), GPIO_OUT_LOW) /* C1 BC1.2 Power */
GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT) /* C1 BC1.2 Detect */
GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT | /* C1 DP Hotplug Detect */
GPIO_SEL_1P8V)
-GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_OUT_LOW) /* OTG ID */
+
+/*
+ * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it
+ * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it
+ * high.
+ */
+GPIO(USB2_OTG_ID, PIN(8, 3), GPIO_ODR_LOW) /* OTG ID */
/* LED */
GPIO(LED_1_PWR_WHITE_L, PIN(C, 3), GPIO_OUT_HIGH)