Fleex: Update EC GPIOs for Fleex EVT

This change sets GPIO83 to the new USB_C0_PD_RST.  The GPIO flags are
set according to whether the board is a proto (where it is acting as
USB_OTG and needs to be open drain) or EVT (where it is an active-high
signal).  This also adds CAM_SOC_EC_SYNC as an input for now.

BRANCH=None
BUG=b:112458646
TEST=Loaded onto fleex proto to verify proto board was detected and
USB_OTG set to open drain

Change-Id: Iffa4762f46d545a0431a27f2c1893f219695d367
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180354
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

2 files changed, 38 insertions, 7 deletions

diff --git a/board/fleex/board.c b/board/fleex/board.c
index 9a794c518a..11564aa73d 100644
--- a/board/fleex/board.c
+++ b/board/fleex/board.c
@@ -243,3 +243,33 @@ void lid_angle_peripheral_enable(int enable)
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 }
 #endif
+
+/*
+ * Set gpio flags based on board ID, can be removed when proto is no longer
+ * supported
+ */
+static void update_gpios_from_board_id(void)
+{
+	uint32_t board_id = 0;
+
+	/* Errors will count as board_id 0 */
+	cbi_get_board_version(&board_id);
+
+	if (board_id == 0) {
+		/*
+		 * USB2_OTG_ID is a 1.8V pin on the SoC side with an internal
+		 * pull-up. However, it is 3.3V on the EC side. So, configure
+		 * it as ODR so that the EC never drives it high.
+		 */
+		gpio_set_flags(GPIO_USB_C0_PD_RST, GPIO_ODR_LOW);
+	} else {
+		int flags = GPIO_OUTPUT;
+
+		if (!system_is_reboot_warm() && !system_jumped_to_this_image())
+			flags |= GPIO_LOW;
+
+		gpio_set_flags(GPIO_USB_C0_PD_RST, flags);
+	}
+}
+
+DECLARE_HOOK(HOOK_INIT, update_gpios_from_board_id, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
index 4170c84ee2..3b340a8a64 100644
--- a/board/fleex/gpio.inc
+++ b/board/fleex/gpio.inc
@@ -101,6 +101,13 @@ GPIO(EN_USB_A0_5V,	 PIN(6, 7), GPIO_OUT_LOW)	/* Enable A0 5V Charging */
 GPIO(EN_USB_A1_5V,	 PIN(9, 6), GPIO_OUT_LOW)	/* Enable A1 5V Charging */
 GPIO(USB_A0_CHARGE_EN_L, PIN(A, 2), GPIO_OUT_HIGH)	/* Enable A0 1.5A Charging */
 GPIO(USB_A1_CHARGE_EN_L, PIN(A, 0), GPIO_OUT_HIGH)	/* Enable A1 1.5A Charging */
+/*
+ * TODO(b/112756630): octopus: add reset logic for C0 TCPC
+ *
+ * Proto USB2_OTG_ID pin
+ * Configure as default since on proto boards this pin should not be driven high
+ */
+GPIO(USB_C0_PD_RST,	 PIN(8, 3), GPIO_DEFAULT)	/* C0 PD Reset */
 GPIO(USB_C0_BC12_VBUS_ON,   PIN(6, 3), GPIO_OUT_LOW)	/* C0 BC1.2 Power */
 GPIO(USB_C0_BC12_CHG_DET_L, PIN(9, 5), GPIO_INPUT)	/* C0 BC1.2 Detect */
 GPIO(USB_C0_HPD_1V8_ODL, PIN(C, 5), GPIO_INPUT |	/* C0 DP Hotplug Detect */
@@ -111,13 +118,6 @@ GPIO(USB_C1_BC12_CHG_DET_L, PIN(E, 4), GPIO_INPUT)	/* C1 BC1.2 Detect */
 GPIO(USB_C1_HPD_1V8_ODL, PIN(C, 6), GPIO_INPUT |	/* C1 DP Hotplug Detect */
 				    GPIO_SEL_1P8V)
 
-/*
- * USB2_OTG_ID is 1.8V pin on the SoC side with an internal pull-up. However, it
- * 3.3V on the EC side. So, configure it as ODR so that the EC never drives it
- * high.
- */
-GPIO(USB2_OTG_ID,	 PIN(8, 3), GPIO_ODR_LOW)	/* OTG ID */
-
 /* LED */
 GPIO(LED_1_PWR_WHITE_L,	 PIN(C, 3), GPIO_OUT_HIGH)
 GPIO(LED_2_CHG_AMBER_L,	 PIN(C, 4), GPIO_OUT_HIGH)
@@ -127,6 +127,7 @@ GPIO(KB_BL_PWR_EN, 	 PIN(6, 2), GPIO_OUT_LOW)
 
 /* Camera */
 GPIO(WFCAM_VSYNC, 	 PIN(0, 3), GPIO_INPUT) 	/* TP only */
+GPIO(CAM_SOC_EC_SYNC,	 PIN(9, 4), GPIO_INPUT)		/* Proto: NC WoV pin */
 
 /* Keyboard pins */
 ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)	/* KSI_00-01 */