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| author | Moritz Fischer <moritz.fischer@ettus.com> | 2018-09-10 13:45:30 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-28 06:26:08 -0700 |
| commit | acfd14a3345e7b7fa3fd3520c5b399fe6229d3cc (patch) | |
| tree | a41ec808656f67abe2431aa1acff4f7f86875930 | |
| parent | 78ea73cde13cda17a9b6240cc0b288c95a2f6482 (diff) | |
| download | chrome-ec-acfd14a3345e7b7fa3fd3520c5b399fe6229d3cc.tar.gz | |
Make ADCs on STM32F4 work
Make ADCs on STM32F4 chips work by reusing most of the STM32F3 code
with the addition of SWSTART=1 bit in adc_read_channel.
The SWSTART=1 is most likely also required for the F3, but could
not be tested on actual hardware.
BUG=none
BRANCH=master
TEST=Build for nucleo-411RE and check measurements
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Iea4f961b22119b5f2c1ee71295ec3ef1b7b7232c
Reviewed-on: https://chromium-review.googlesource.com/1217603
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
| -rw-r--r-- | chip/stm32/adc-stm32f3.c | 20 | ||||
| l--------- | chip/stm32/adc-stm32f4.c | 1 | ||||
| -rw-r--r-- | chip/stm32/clock-stm32f4.c | 6 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 7 |
4 files changed, 26 insertions, 8 deletions
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 28a50916c6..6e22c49ac3 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -195,8 +195,12 @@ int adc_read_channel(enum adc_channel ch) /* Clear EOC bit */ STM32_ADC_SR &= ~(1 << 1); - /* Start conversion */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + /* Start conversion (Note: For now only confirmed on F4) */ +#if defined(CHIP_FAMILY_STM32F4) + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; +#else + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; +#endif /* Wait for EOC bit set */ deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; @@ -233,21 +237,21 @@ static void adc_init(void) if (!adc_powered()) { /* Power on ADC module */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; /* Reset calibration */ - STM32_ADC_CR2 |= (1 << 3); /* RSTCAL */ - while (STM32_ADC_CR2 & (1 << 3)) + STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) ; /* A/D Calibrate */ - STM32_ADC_CR2 |= (1 << 2); /* CAL */ - while (STM32_ADC_CR2 & (1 << 2)) + STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) ; } /* Set right alignment */ - STM32_ADC_CR2 &= ~(1 << 11); + STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; /* Set sample time of all channels */ STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c new file mode 120000 index 0000000000..5e375b9dbf --- /dev/null +++ b/chip/stm32/adc-stm32f4.c @@ -0,0 +1 @@ +adc-stm32f3.c
\ No newline at end of file diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index ed4ffe6848..5ece4fde27 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -227,6 +227,12 @@ void clock_enable_module(enum module_id module, int enable) STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN); } return; + } else if (module == MODULE_ADC) { + if (enable) + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADC1EN; + else + STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADC1EN; + return; } CPRINTS("Module %d is not supported for clock %s\n", diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 5333c8e07c..9c41656e27 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1372,6 +1372,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_FMPI2C4EN (1 << 24) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_APB2ENR_ADC1EN (1 << 8) /* STM32F4 */ #define STM32_RCC_PB2_USART6 (1 << 5) #define STM32_RCC_SYSCFGEN (1 << 14) @@ -2180,6 +2181,12 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) #define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) #define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON (1 << 0) +#define STM32_ADC_CR2_CONT (1 << 1) +#define STM32_ADC_CR2_CAL (1 << 2) +#define STM32_ADC_CR2_RSTCAL (1 << 3) +#define STM32_ADC_CR2_ALIGN (1 << 11) +#define STM32_ADC_CR2_SWSTART (1 << 30) #define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) #define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) #define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) |