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| author | li feng <li1.feng@intel.com> | 2018-01-24 17:20:42 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-19 03:12:04 -0700 |
| commit | f3700fe58696c917c953d091d0fcfc2077f54b98 (patch) | |
| tree | 72a056039dcec436ef2c8588dd9216f419905e94 | |
| parent | bd20798aa85a0bbb2dca3b9ce9a9d563e215fa0c (diff) | |
| download | chrome-ec-f3700fe58696c917c953d091d0fcfc2077f54b98.tar.gz | |
ish: gpio: gpio macro added
BUG=b:116451255
BRANCH=none
TEST=Tested on Atlas board with ISH.
Change-Id: I6b3913d2374e68e9522927ad5609f2867cc56f34
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/885007
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
| -rw-r--r-- | chip/ish/config_chip.h | 6 | ||||
| -rw-r--r-- | chip/ish/registers.h | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 224f63b627..7b682bd3fe 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -72,8 +72,8 @@ /* Note: ISH does not use the LPC bus but the protocol. */ #define CONFIG_HOSTCMD_LPC -/* GPIO - to be implemented */ -#define GPIO_PIN(index) (index) -#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) +/* Macro used with gpio.inc, ISH only has port 0 */ +#define GPIO_PIN(index) 0, (1 << (index)) +#define GPIO_PIN_MASK(m) .port = 0, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 466a657089..74306e9159 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -11,6 +11,9 @@ #ifndef __ASSEMBLER__ #include "common.h" +/* ISH GPIO has only one port */ +#define DUMMY_GPIO_BANK 0 + /* * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port). */ @@ -20,6 +23,7 @@ enum ish_i2c_port { ISH_I2C2 = 2, /* Controller 2 */ I2C_PORT_COUNT, }; + #endif #define ISH_I2C_PORT_COUNT I2C_PORT_COUNT |